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Generalise 65c02 behaviour.

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Partly to convince myself:
1. this change alters behaviour of `CycleAddXToAddressLowRead`
2. which affects only `AbsoluteXw` and the 65c02-specific `JMP (abs, x)`;
3. `AbsoluteXw` is then used only by `AbsoluteXWrite` and `AbsoluteXReadModifyWrite`;
4. `AbsoluteXWrite` is used for abs, x addressing by `SHY`, `STA` and `STZ`;
5. `AbsoluteXReadModifyWrite` is used for `ASL`, `ASO`, `ROL`, `RLA`, `LSR`, `LSE`, `ROR`, `RRA`, `DEC`, `DCP`, `INC` and `INS`.

... though many of the latter are replaced by instance of `FastAbsoluteXReadModifyWrite` for the 65c02 which don't include a dummy
access at all if the page boundary is crossed so the issue is moot.
This commit is contained in:
Thomas Harte 2023-12-20 15:39:34 -05:00
parent f25aaf2bb3
commit bf5ed98f35
3 changed files with 9 additions and 14 deletions
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7
Processors/6502/Implementation/6502Implementation.hpp
View File

@ -544,7 +544,7 @@ template <Personality personality, typename T, bool uses_ready_line> void Proces
break;
}
continue;
case CycleAddXToAddressLowReadSTA:
case CycleAddXToAddressLowRead:
next_address_.full = address_.full + x_;
address_.halves.low = next_address_.halves.low;
@ -559,11 +559,6 @@ template <Personality personality, typename T, bool uses_ready_line> void Proces
throwaway_read(pc_.full - 1);
}
break;
case CycleAddXToAddressLowRead:
next_address_.full = address_.full + x_;
address_.halves.low = next_address_.halves.low;
page_crossing_stall_read();
break;
case CycleAddYToAddressLow:
next_address_.full = address_.full + y_;
address_.halves.low = next_address_.halves.low;

4
Processors/6502/Implementation/6502Storage.cpp
View File

@ -18,7 +18,6 @@ using namespace CPU::MOS6502;
#define AbsoluteXr CycleLoadAddressAbsolute, CycleAddXToAddressLow, OperationCorrectAddressHigh
#define AbsoluteYr CycleLoadAddressAbsolute, CycleAddYToAddressLow, OperationCorrectAddressHigh
#define AbsoluteXw CycleLoadAddressAbsolute, CycleAddXToAddressLowRead, OperationCorrectAddressHigh
#define AbsoluteXwSTA CycleLoadAddressAbsolute, CycleAddXToAddressLowReadSTA, OperationCorrectAddressHigh
#define AbsoluteYw CycleLoadAddressAbsolute, CycleAddYToAddressLowRead, OperationCorrectAddressHigh
#define Zero OperationLoadAddressZeroPage
#define ZeroX CycleLoadAddessZeroX
@ -44,7 +43,6 @@ using namespace CPU::MOS6502;
#define AbsoluteWrite(op) Program(Absolute, Write(op))
#define AbsoluteXWrite(op) Program(AbsoluteXw, Write(op))
#define AbsoluteXWriteSTA(op) Program(AbsoluteXwSTA, Write(op))
#define AbsoluteYWrite(op) Program(AbsoluteYw, Write(op))
#define ZeroWrite(op) Program(Zero, Write(op))
#define ZeroXWrite(op) Program(ZeroX, Write(op))
@ -164,7 +162,7 @@ ProcessorStorage::ProcessorStorage(Personality personality) {
/* 0x96 STX zpg, y */ ZeroYWrite(OperationSTX), /* 0x97 SAX zpg, y */ ZeroYWrite(OperationSAX),
/* 0x98 TYA */ Program(OperationTYA), /* 0x99 STA abs, y */ AbsoluteYWrite(OperationSTA),
/* 0x9a TXS */ Program(OperationTXS), /* 0x9b SHS abs, y */ AbsoluteYWrite(OperationSHS),
/* 0x9c SHY abs, x */ AbsoluteXWrite(OperationSHY), /* 0x9d STA abs, x */ AbsoluteXWriteSTA(OperationSTA),
/* 0x9c SHY abs, x */ AbsoluteXWrite(OperationSHY), /* 0x9d STA abs, x */ AbsoluteXWrite(OperationSTA),
/* 0x9e SHX abs, y */ AbsoluteYWrite(OperationSHX), /* 0x9f SHA abs, y */ AbsoluteYWrite(OperationSHA),
/* 0xa0 LDY # */ Immediate(OperationLDY), /* 0xa1 LDA x, ind */ IndexedIndirectRead(OperationLDA),
/* 0xa2 LDX # */ Immediate(OperationLDX), /* 0xa3 LAX x, ind */ IndexedIndirectRead(OperationLAX),

12
Processors/6502/Implementation/6502Storage.hpp
View File

@ -73,14 +73,16 @@ class ProcessorStorage {
CycleAddXToAddressLow, // calculates address_ + x and stores it to next_address_; copies next_address_.l back to address_.l; 6502: if address_ now does not equal next_address_, schedules a throwaway read from address_; 65C02: schedules a throaway read from PC-1
CycleAddYToAddressLow, // calculates address_ + y and stores it to next_address_; copies next_address_.l back to address_.l; 6502: if address_ now does not equal next_address_, schedules a throwaway read from address_; 65C02: schedules a throaway read from PC-1
CycleAddXToAddressLowRead, // calculates address_ + x and stores it to next_address; copies next_address.l back to address_.l; 6502: schedules a throwaway read from address_; 65C02: schedules a throaway read from PC-1
CycleAddYToAddressLowRead, // calculates address_ + y and stores it to next_address; copies next_address.l back to address_.l; 6502: schedules a throwaway read from address_; 65C02: schedules a throaway read from PC-1
OperationCorrectAddressHigh, // copies next_address_ to address_
// Implements 65c02-compatible version of CycleAddXToAddressLowRead specialised for STA; on that processor
// a non-page-crossing `STA abs, x` acts exactly like a 6502, doing a read of the target address before
// the write, but a page-crossing store instead performs throaway read from PC-1.
CycleAddXToAddressLowReadSTA,
// Calculates address_ + x and stores it to next_address; copies next_address.l back to address_.l.
//
// 6502: schedules a throwaway read from address_.
// 65C02: schedules a throaway read from PC-1 if a page boundary was crossed;
// otherwise does as per the 6502.
//
CycleAddXToAddressLowRead,
OperationIncrementPC, // increments the PC
CycleFetchOperandFromAddress, // fetches operand_ from address_