From bfd0b683bf9b682cb9f2e432d89c061c31ccdec5 Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Tue, 14 Jun 2022 17:04:11 -0400
Subject: [PATCH] Extend MOVE.b fix to cover MOVE.w.

---
 .../Implementation/68000Mk2Implementation.hpp | 81 ++++++++++++-------
 1 file changed, 53 insertions(+), 28 deletions(-)

diff --git a/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp b/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
index 025ad01d7..60d3fe521 100644
--- a/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
+++ b/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
@@ -192,11 +192,17 @@ enum ExecutionState: int {
 	PEA_np_nS_ns,		// Used to complete (An), (d16, [An/PC]) and (d8, [An/PC], Xn).
 	PEA_np_nS_ns_np,	// Used to complete (xxx).w and (xxx).l
 
-	AddressingDispatch(MOVE_b),	MOVE_b_AbsoluteLong_prefetch_first,
+	MOVE_b, MOVE_w,
+	AddressingDispatch(MOVE_bw),	MOVE_bw_AbsoluteLong_prefetch_first,
 };
 
 #undef AddressingDispatch
 
+/// @returns The proper select lines for @c instruction's operand size, assuming it is either byte or word.
+template <typename InstructionT> Microcycle::OperationT data_select(const InstructionT &instruction) {
+	return Microcycle::OperationT(1 << int(instruction.operand_size()));
+}
+
 // MARK: - The state machine.
 
 template <class BusHandler, bool dtack_is_implicit, bool permit_overrun, bool signal_will_perform>
@@ -748,7 +754,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 
 				StdCASE(MOVEb,		perform_state_ = MOVE_b);
 				Duplicate(MOVEAw, MOVEw)
-				StdCASE(MOVEw,		perform_state_ = MOVE);
+				StdCASE(MOVEw,		perform_state_ = MOVE_w);
 				Duplicate(MOVEAl, MOVEl)
 				StdCASE(MOVEl,		perform_state_ = MOVE);
 
@@ -1115,8 +1121,20 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 			operand_[next_operand_] = registers_[instruction_.lreg(next_operand_)];
 		MoveToNextOperand(FetchOperand_l);
 
-		BeginStateMode(MOVE_b, DataRegisterDirect):
-			registers_[instruction_.lreg(1)].b = operand_[1].b;
+		BeginStateMode(MOVE_bw, AddressRegisterDirect):
+			registers_[instruction_.reg(1)] = operand_[1];
+			Prefetch();
+		MoveToStateSpecific(Decode);
+
+		BeginStateMode(MOVE_bw, DataRegisterDirect): {
+			const uint32_t write_mask = size_masks[int(instruction_.operand_size())];
+			const int reg = instruction_.lreg(1);
+
+			registers_[reg].l =
+				(operand_[1].l & write_mask) |
+				(registers_[reg].l & ~write_mask);
+			}
+
 			Prefetch();
 		MoveToStateSpecific(Decode);
 
@@ -1141,10 +1159,10 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 			Access(operand_[next_operand_].low);	// nr
 		MoveToNextOperand(FetchOperand_bw);
 
-		BeginStateMode(MOVE_b, AddressRegisterIndirect):
+		BeginStateMode(MOVE_bw, AddressRegisterIndirect):
 			effective_address_[1].l = registers_[8 + instruction_.reg(1)].l;
 			SetDataAddress(effective_address_[1].l);
-			SetupDataAccess(0, Microcycle::SelectByte);
+			SetupDataAccess(0, data_select(instruction_));
 
 			Access(operand_[next_operand_].low);	// nw
 			Prefetch();								// np
@@ -1186,13 +1204,15 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 			Access(operand_[next_operand_].low);	// nr
 		MoveToNextOperand(FetchOperand_bw);
 
-		BeginStateMode(MOVE_b, AddressRegisterIndirectWithPostincrement):
+		BeginStateMode(MOVE_bw, AddressRegisterIndirectWithPostincrement):
 			effective_address_[1].l = registers_[8 + instruction_.reg(1)].l;
-			registers_[8 + instruction_.reg(1)].l += address_increments[0][instruction_.reg(1)];
-			SetDataAddress(effective_address_[1].l);
-			SetupDataAccess(0, Microcycle::SelectByte);
+			registers_[8 + instruction_.reg(next_operand_)].l +=
+				address_increments[int(instruction_.operand_size())][instruction_.reg(1)];
 
+			SetDataAddress(effective_address_[1].l);
+			SetupDataAccess(0, data_select(instruction_));
 			Access(operand_[next_operand_].low);	// nw
+
 			Prefetch();								// np
 		MoveToStateSpecific(Decode);
 
@@ -1226,11 +1246,12 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 			Access(operand_[next_operand_].low);	// nr
 		MoveToNextOperand(FetchOperand_bw);
 
-		BeginStateMode(MOVE_b, AddressRegisterIndirectWithPredecrement):
-			registers_[8 + instruction_.reg(1)].l -= address_increments[0][instruction_.reg(1)];
+		BeginStateMode(MOVE_bw, AddressRegisterIndirectWithPredecrement):
+			registers_[8 + instruction_.reg(1)].l -= address_increments[int(instruction_.operand_size())][instruction_.reg(1)];
 			effective_address_[1].l = registers_[8 + instruction_.reg(1)].l;
+
 			SetDataAddress(effective_address_[1].l);
-			SetupDataAccess(0, Microcycle::SelectByte);
+			SetupDataAccess(0, data_select(instruction_));
 
 			Prefetch();								// np
 			Access(operand_[next_operand_].low);	// nw
@@ -1270,13 +1291,13 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 			Access(operand_[next_operand_].low);	// nr
 		MoveToNextOperand(FetchOperand_bw);
 
-		BeginStateMode(MOVE_b, AddressRegisterIndirectWithDisplacement):
+		BeginStateMode(MOVE_bw, AddressRegisterIndirectWithDisplacement):
 			effective_address_[1].l =
 				registers_[8 + instruction_.reg(1)].l +
 				uint32_t(int16_t(prefetch_.w));
 
 			SetDataAddress(effective_address_[1].l);
-			SetupDataAccess(0, Microcycle::SelectByte);
+			SetupDataAccess(0, data_select(instruction_));
 
 			Prefetch();								// np
 			Access(operand_[next_operand_].low);	// nw
@@ -1331,13 +1352,13 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 			Access(operand_[next_operand_].low);	// nr
 		MoveToNextOperand(FetchOperand_bw);
 
-		BeginStateMode(MOVE_b, ProgramCounterIndirectWithDisplacement):
+		BeginStateMode(MOVE_bw, ProgramCounterIndirectWithDisplacement):
 			effective_address_[1].l =
 				program_counter_.l - 2 +
 				uint32_t(int16_t(prefetch_.w));
 
 			SetDataAddress(effective_address_[1].l);
-			SetupDataAccess(0, Microcycle::SelectByte);
+			SetupDataAccess(0, data_select(instruction_));
 
 			Prefetch();								// np
 			Access(operand_[next_operand_].low);	// nw
@@ -1398,11 +1419,11 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 			Access(operand_[next_operand_].low);	// nr
 		MoveToNextOperand(FetchOperand_bw);
 
-		BeginStateMode(MOVE_b, AddressRegisterIndirectWithIndex8bitDisplacement):
+		BeginStateMode(MOVE_bw, AddressRegisterIndirectWithIndex8bitDisplacement):
 			effective_address_[1].l = d8Xn(registers_[8 + instruction_.reg(1)].l);
 
 			SetDataAddress(effective_address_[1].l);
-			SetupDataAccess(0, Microcycle::SelectByte);
+			SetupDataAccess(0, data_select(instruction_));
 
 			IdleBus(1);								// n
 			Prefetch();								// np
@@ -1462,11 +1483,11 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 			Access(operand_[next_operand_].low);	// nr
 		MoveToNextOperand(FetchOperand_bw);
 
-		BeginStateMode(MOVE_b, ProgramCounterIndirectWithIndex8bitDisplacement):
+		BeginStateMode(MOVE_bw, ProgramCounterIndirectWithIndex8bitDisplacement):
 			effective_address_[1].l = d8Xn(program_counter_.l - 2);
 
 			SetDataAddress(effective_address_[1].l);
-			SetupDataAccess(0, Microcycle::SelectByte);
+			SetupDataAccess(0, data_select(instruction_));
 
 			IdleBus(1);								// n
 			Prefetch();								// np
@@ -1527,11 +1548,11 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 			Access(operand_[next_operand_].low);	// nr
 		MoveToNextOperand(FetchOperand_bw);
 
-		BeginStateMode(MOVE_b, AbsoluteShort):
+		BeginStateMode(MOVE_bw, AbsoluteShort):
 			effective_address_[1].l = uint32_t(int16_t(prefetch_.w));
 
 			SetDataAddress(effective_address_[1].l);
-			SetupDataAccess(0, Microcycle::SelectByte);
+			SetupDataAccess(0, data_select(instruction_));
 
 			Prefetch();								// np
 			Access(operand_[next_operand_].low);	// nw
@@ -1577,19 +1598,19 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 			Access(operand_[next_operand_].low);	// nr
 		MoveToNextOperand(FetchOperand_bw);
 
-		BeginStateMode(MOVE_b, AbsoluteLong):
+		BeginStateMode(MOVE_bw, AbsoluteLong):
 			Prefetch();								// np
 
 			effective_address_[1].l = prefetch_.l;
 
 			SetDataAddress(effective_address_[1].l);
-			SetupDataAccess(0, Microcycle::SelectByte);
+			SetupDataAccess(0, data_select(instruction_));
 
 			switch(instruction_.mode(0)) {
 				case Mode::AddressRegisterDirect:
 				case Mode::DataRegisterDirect:
 				case Mode::ImmediateData:
-					MoveToStateSpecific(MOVE_b_AbsoluteLong_prefetch_first);
+					MoveToStateSpecific(MOVE_bw_AbsoluteLong_prefetch_first);
 
 				default: break;
 			}
@@ -1599,7 +1620,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 			Prefetch();								// np
 		MoveToStateSpecific(Decode);
 
-		BeginState(MOVE_b_AbsoluteLong_prefetch_first):
+		BeginState(MOVE_bw_AbsoluteLong_prefetch_first):
 			Prefetch();								// np
 			Access(operand_[next_operand_].low);	// nw
 			Prefetch();								// np
@@ -1876,7 +1897,11 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 
 		BeginState(MOVE_b):
 			PerformSpecific(MOVEb);
-		MoveToAddressingMode(MOVE_b, instruction_.mode(1));
+		MoveToAddressingMode(MOVE_bw, instruction_.mode(1));
+
+		BeginState(MOVE_w):
+			PerformSpecific(MOVEw);
+		MoveToAddressingMode(MOVE_bw, instruction_.mode(1));
 
 		//
 		// [ABCD/SBCD/SUBX/ADDX] (An)-, (An)-