diff --git a/InstructionSets/M68k/Decoder.cpp b/InstructionSets/M68k/Decoder.cpp index 83c3e55a5..3ac170c67 100644 --- a/InstructionSets/M68k/Decoder.cpp +++ b/InstructionSets/M68k/Decoder.cpp @@ -502,6 +502,11 @@ template ::OpT op> uint32_t Predecoder::invali return ~OneOperandMask< Imm >::value; + + case OpT(Operation::MOVEfromCCR): + return ~OneOperandMask< + AlterableAddressingModesNoAn + >::value; } // @@ -992,6 +997,12 @@ template ::OpT op, bool validate> Preinstruction Pred // case OpT(Operation::RTD): return validated(AddressingMode::ImmediateData); + + // + // MARK: MOVE from CCR. + // + case OpT(Operation::MOVEfromCCR): + return validated(combined_mode(ea_mode, ea_register), ea_register); } // @@ -1357,6 +1368,9 @@ Preinstruction Predecoder::decode4(uint16_t instruction) { // 4-94 (p198) case 0xc40: DecodeReq(model >= Model::M68020, Op::DIVSl); + // 4-121 (p225) + case 0x2c0: DecodeReq(model >= Model::M68010, Op::MOVEfromCCR); + default: break; } diff --git a/InstructionSets/M68k/Instruction.cpp b/InstructionSets/M68k/Instruction.cpp index 1c76e97cc..588051ab9 100644 --- a/InstructionSets/M68k/Instruction.cpp +++ b/InstructionSets/M68k/Instruction.cpp @@ -102,6 +102,7 @@ const char *_to_string(Operation operation, bool is_quick) { case Operation::MOVEtoSR: return "MOVEtoSR"; case Operation::MOVEfromSR: return "MOVEfromSR"; case Operation::MOVEtoCCR: return "MOVEtoCCR"; + case Operation::MOVEfromCCR: return "MOVEfromCCR"; case Operation::MOVEtoUSP: return "MOVEtoUSP"; case Operation::MOVEfromUSP: return "MOVEfromUSP";