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mirror of https://github.com/TomHarte/CLK.git synced 2024-10-01 13:58:20 +00:00

Converted the ZX80/81 video component into a ClockReceiver. As it happens, it's most convenient to take the half-cycle bus here.

This commit is contained in:
Thomas Harte 2017-07-22 23:02:28 -04:00
parent b0c2325adc
commit c2a7dffa7d
3 changed files with 11 additions and 10 deletions

View File

@ -29,9 +29,9 @@ Video::Video() :
crt_->set_visible_area(Outputs::CRT::Rect(0.1f, 0.1f, 0.8f, 0.8f)); crt_->set_visible_area(Outputs::CRT::Rect(0.1f, 0.1f, 0.8f, 0.8f));
} }
void Video::run_for_cycles(int number_of_cycles) { void Video::run_for(const HalfCycles &half_cycles) {
// Just keep a running total of the amount of time that remains owed to the CRT. // Just keep a running total of the amount of time that remains owed to the CRT.
cycles_since_update_ += (unsigned int)number_of_cycles << 1; cycles_since_update_ += (unsigned int)int(half_cycles);
} }
void Video::flush() { void Video::flush() {

View File

@ -10,6 +10,7 @@
#define Machines_ZX8081_Video_hpp #define Machines_ZX8081_Video_hpp
#include "../../Outputs/CRT/CRT.hpp" #include "../../Outputs/CRT/CRT.hpp"
#include "../../Components/ClockReceiver.hpp"
namespace ZX8081 { namespace ZX8081 {
@ -23,15 +24,15 @@ namespace ZX8081 {
a 1-bit graphic and output over the next 4 cycles, picking between the white level a 1-bit graphic and output over the next 4 cycles, picking between the white level
and the black level. and the black level.
*/ */
class Video { class Video: public ClockReceiver<Video> {
public: public:
/// Constructs an instance of the video feed; a CRT is also created. /// Constructs an instance of the video feed; a CRT is also created.
Video(); Video();
/// @returns The CRT this video feed is feeding. /// @returns The CRT this video feed is feeding.
std::shared_ptr<Outputs::CRT::CRT> get_crt(); std::shared_ptr<Outputs::CRT::CRT> get_crt();
/// Advances time by @c number_of_cycles cycles. /// Advances time by @c cycles.
void run_for_cycles(int number_of_cycles); void run_for(const HalfCycles &);
/// Forces output to catch up to the current output position. /// Forces output to catch up to the current output position.
void flush(); void flush();

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@ -34,23 +34,23 @@ int Machine::perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) {
horizontal_counter_ += cycle.length; horizontal_counter_ += cycle.length;
if(previous_counter < vsync_start_cycle_ && horizontal_counter_ >= vsync_start_cycle_) { if(previous_counter < vsync_start_cycle_ && horizontal_counter_ >= vsync_start_cycle_) {
video_->run_for_cycles(vsync_start_cycle_ - previous_counter); video_->run_for(Cycles(vsync_start_cycle_ - previous_counter));
set_hsync(true); set_hsync(true);
line_counter_ = (line_counter_ + 1) & 7; line_counter_ = (line_counter_ + 1) & 7;
if(nmi_is_enabled_) { if(nmi_is_enabled_) {
set_non_maskable_interrupt_line(true); set_non_maskable_interrupt_line(true);
} }
video_->run_for_cycles(horizontal_counter_ - vsync_start_cycle_); video_->run_for(Cycles(horizontal_counter_ - vsync_start_cycle_));
} else if(previous_counter < vsync_end_cycle_ && horizontal_counter_ >= vsync_end_cycle_) { } else if(previous_counter < vsync_end_cycle_ && horizontal_counter_ >= vsync_end_cycle_) {
video_->run_for_cycles(vsync_end_cycle_ - previous_counter); video_->run_for(Cycles(vsync_end_cycle_ - previous_counter));
set_hsync(false); set_hsync(false);
if(nmi_is_enabled_) { if(nmi_is_enabled_) {
set_non_maskable_interrupt_line(false); set_non_maskable_interrupt_line(false);
set_wait_line(false); set_wait_line(false);
} }
video_->run_for_cycles(horizontal_counter_ - vsync_end_cycle_); video_->run_for(Cycles(horizontal_counter_ - vsync_end_cycle_));
} else { } else {
video_->run_for_cycles(cycle.length); video_->run_for(Cycles(cycle.length));
} }
if(is_zx81_) horizontal_counter_ %= 207; if(is_zx81_) horizontal_counter_ %= 207;