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Merge pull request #900 from TomHarte/SpeccyTiming
Further tweaks Spectrum timing.
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commit
c2fde2b147
@ -53,14 +53,14 @@ template <VideoTiming timing> class Video {
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// Number of lines comprising a whole frame. Will be 311 or 312.
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// Number of lines comprising a whole frame. Will be 311 or 312.
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int lines_per_frame;
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int lines_per_frame;
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// Number of cycles after first pixel fetch at which interrupt is first signalled.
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int interrupt_time;
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// Number of cycles before first pixel fetch that contention starts to be applied.
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// Number of cycles before first pixel fetch that contention starts to be applied.
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int contention_leadin;
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int contention_leadin;
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// Period in a line for which contention is applied.
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// Period in a line for which contention is applied.
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int contention_duration;
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int contention_duration;
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// Number of cycles after first pixel fetch at which interrupt is first signalled.
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int interrupt_time;
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// Contention to apply, in half-cycles, as a function of number of half cycles since
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// Contention to apply, in half-cycles, as a function of number of half cycles since
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// contention began.
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// contention began.
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int delays[16];
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int delays[16];
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@ -88,11 +88,15 @@ template <VideoTiming timing> class Video {
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.cycles_per_line = 228 * 2,
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.cycles_per_line = 228 * 2,
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.lines_per_frame = 311,
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.lines_per_frame = 311,
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.interrupt_time = 56545 * 2,
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// i.e. video fetching begins six cycles after the start of the
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// contended memory pattern below; that should put a clear two
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.contention_leadin = 2 * 2, // TODO: is this 2? Or 4? Or... ?
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// cycles between a Z80 access and the first video fetch.
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.contention_leadin = 6 * 2,
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.contention_duration = 129 * 2,
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.contention_duration = 129 * 2,
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// i.e. interrupt is first signalled 14368 cycles before the first video fetch.
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.interrupt_time = (228*311 - 14368) * 2,
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.delays = {
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.delays = {
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2, 1,
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2, 1,
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0, 0,
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0, 0,
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@ -311,7 +315,9 @@ template <VideoTiming timing> class Video {
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}
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}
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const int time_into_line = delay_time % timings.cycles_per_line;
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const int time_into_line = delay_time % timings.cycles_per_line;
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if(time_into_line >= timings.contention_duration) return 0;
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if(time_into_line >= timings.contention_duration) {
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return 0;
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}
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return timings.delays[time_into_line & 15];
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return timings.delays[time_into_line & 15];
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}
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}
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@ -184,24 +184,29 @@ template<Model model> class ConcreteMachine:
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forceinline HalfCycles perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) {
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forceinline HalfCycles perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) {
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using PartialMachineCycle = CPU::Z80::PartialMachineCycle;
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using PartialMachineCycle = CPU::Z80::PartialMachineCycle;
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HalfCycles delay(0);
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const uint16_t address = cycle.address ? *cycle.address : 0x0000;
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const uint16_t address = cycle.address ? *cycle.address : 0x0000;
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switch(cycle.operation) {
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default: break;
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case PartialMachineCycle::ReadOpcodeStart:
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case PartialMachineCycle::ReadStart:
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case PartialMachineCycle::WriteStart:
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// Apply contention if necessary.
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// Apply contention if necessary.
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//
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if(
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is_contended_[address >> 14] &&
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cycle.operation >= PartialMachineCycle::ReadOpcodeStart &&
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cycle.operation <= PartialMachineCycle::WriteStart) {
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// Assumption here: the trigger for the ULA inserting a delay is the falling edge
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// Assumption here: the trigger for the ULA inserting a delay is the falling edge
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// of MREQ, which is always half a cycle into a read or write.
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// of MREQ, which is always half a cycle into a read or write.
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//
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//
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// TODO: somehow provide that information in the PartialMachineCycle?
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// TODO: somehow provide that information in the PartialMachineCycle?
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if(is_contended_[address >> 14]) {
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delay = video_.last_valid()->access_delay(video_.time_since_flush() + HalfCycles(1));
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const HalfCycles delay = video_.last_valid()->access_delay(video_.time_since_flush() + HalfCycles(1));
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advance(cycle.length + delay);
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return delay;
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}
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}
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break;
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// For all other machine cycles, model the action as happening at the end of the machine cycle;
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// that means advancing time now.
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advance(cycle.length);
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switch(cycle.operation) {
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default: break;
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case PartialMachineCycle::ReadOpcode:
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case PartialMachineCycle::ReadOpcode:
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// Fast loading: ROM version.
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// Fast loading: ROM version.
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@ -224,7 +229,7 @@ template<Model model> class ConcreteMachine:
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*cycle.value = read_pointers_[address >> 14][address];
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*cycle.value = read_pointers_[address >> 14][address];
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if(is_contended_[address >> 14]) {
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if(is_contended_[address >> 14]) {
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video_.last_valid()->set_last_contended_area_access(*cycle.value);
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video_->set_last_contended_area_access(*cycle.value);
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}
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}
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break;
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break;
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@ -238,7 +243,7 @@ template<Model model> class ConcreteMachine:
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// Fill the floating bus buffer if this write is within the contended area.
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// Fill the floating bus buffer if this write is within the contended area.
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if(is_contended_[address >> 14]) {
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if(is_contended_[address >> 14]) {
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video_.last_valid()->set_last_contended_area_access(*cycle.value);
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video_->set_last_contended_area_access(*cycle.value);
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}
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}
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break;
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break;
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@ -356,8 +361,7 @@ template<Model model> class ConcreteMachine:
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break;
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break;
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}
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}
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advance(cycle.length + delay);
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return HalfCycles(0);
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return delay;
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}
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}
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private:
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private:
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