6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-19 08:31:11 +00:00
Code Issues Projects Releases Wiki Activity

Imports ANDI, ORI and EORI to SR tests.

Browse Source 
Hence corrects supervisor/user privileges for SR/CCR.
This commit is contained in:
Thomas Harte 2019-06-28 15:05:46 -04:00
parent fd604048db
commit c5039a4719
2 changed files with 86 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

85
OSBindings/Mac/Clock SignalTests/68000Tests.mm
View File

@ -1092,6 +1092,35 @@ class CPU::MC68000::ProcessorStorageTests {
XCTAssertEqual(20, _machine->get_cycle_count()); XCTAssertEqual(20, _machine->get_cycle_count());
} }
// MARK: ANDI SR
- (void)testANDISR_supervisor {
_machine->set_program({
0x027c, 0x0700 // ANDI.W #$700, SR
});
_machine->set_initial_stack_pointer(300);
_machine->run_for_instructions(1);
const auto state = _machine->get_processor_state();
XCTAssertEqual(state.program_counter, 0x1004 + 4);
XCTAssertEqual(20, _machine->get_cycle_count());
}
- (void)testANDISR_user {
_machine->set_program({
0x46fc, 0x0000, // MOVE 0, SR
0x027c, 0x0700 // ANDI.W #$700, SR
});
_machine->run_for_instructions(2);
const auto state = _machine->get_processor_state();
XCTAssertNotEqual(state.program_counter, 0x1008 + 4);
// XCTAssertEqual(34, _machine->get_cycle_count());
}
// MARK: ASL // MARK: ASL
- (void)testASLb_Dn_2 { - (void)testASLb_Dn_2 {
@ -2661,6 +2690,34 @@ class CPU::MC68000::ProcessorStorageTests {
XCTAssertEqual(20, _machine->get_cycle_count()); XCTAssertEqual(20, _machine->get_cycle_count());
} }
// MARK: EORI to SR
- (void)testEORISR_supervisor {
_machine->set_program({
0x0a7c, 0x0700 // EORI.W #$700, SR
});
_machine->set_initial_stack_pointer(300);
_machine->run_for_instructions(1);
const auto state = _machine->get_processor_state();
XCTAssertEqual(state.program_counter, 0x1004 + 4);
XCTAssertEqual(20, _machine->get_cycle_count());
}
- (void)testEORISR_user {
_machine->set_program({
0x46fc, 0x0000, // MOVE 0, SR
0x0a7c, 0x0700 // EORI.W #$700, SR
});
_machine->run_for_instructions(2);
const auto state = _machine->get_processor_state();
XCTAssertNotEqual(state.program_counter, 0x1008 + 4);
// XCTAssertEqual(34, _machine->get_cycle_count());
}
// MARK: EXG // MARK: EXG
- (void)testEXG_D1D2 { - (void)testEXG_D1D2 {
@ -4416,6 +4473,34 @@ class CPU::MC68000::ProcessorStorageTests {
XCTAssertEqual(20, _machine->get_cycle_count()); XCTAssertEqual(20, _machine->get_cycle_count());
} }
// MARK: ORI to SR
- (void)testORISR_supervisor {
_machine->set_program({
0x007c, 0x0700 // ORI.W #$700, SR
});
_machine->set_initial_stack_pointer(300);
_machine->run_for_instructions(1);
const auto state = _machine->get_processor_state();
XCTAssertEqual(state.program_counter, 0x1004 + 4);
XCTAssertEqual(20, _machine->get_cycle_count());
}
- (void)testORISR_user {
_machine->set_program({
0x46fc, 0x0000, // MOVE 0, SR
0x007c, 0x0700 // ORI.W #$700, SR
});
_machine->run_for_instructions(2);
const auto state = _machine->get_processor_state();
XCTAssertNotEqual(state.program_counter, 0x1008 + 4);
// XCTAssertEqual(34, _machine->get_cycle_count());
}
// MARK: PEA // MARK: PEA
- (void)testPEA_A1 { - (void)testPEA_A1 {

2
Processors/68000/Implementation/68000Storage.cpp
View File

@ -978,7 +978,7 @@ struct ProcessorStorageConstructor {
case Decoder::EORI_ORI_ANDI_SR: { case Decoder::EORI_ORI_ANDI_SR: {
// The source used here is always the high word of the prefetch queue. // The source used here is always the high word of the prefetch queue.
program.requires_supervisor = !(instruction & 0x40); program.requires_supervisor = !!(instruction & 0x40);
op(Action::None, seq("np nn nn")); op(Action::None, seq("np nn nn"));
op(Action::PerformOperation, seq("np np")); op(Action::PerformOperation, seq("np np"));
} break; } break;