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Tidy up; provide a notification for bit-change operations.
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@ -56,6 +56,7 @@ template <Model model, typename BusHandler> class Executor {
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void did_shift(int bit_count) {}
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void did_shift(int bit_count) {}
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template <bool did_overflow> void did_divu(uint32_t dividend, uint32_t divisor) {}
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template <bool did_overflow> void did_divu(uint32_t dividend, uint32_t divisor) {}
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template <bool did_overflow> void did_divs(int32_t dividend, int32_t divisor) {}
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template <bool did_overflow> void did_divs(int32_t dividend, int32_t divisor) {}
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void did_bit_op(int bit) {}
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template <typename IntT> void complete_bcc(bool matched_condition, IntT offset);
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template <typename IntT> void complete_bcc(bool matched_condition, IntT offset);
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void complete_dbcc(bool matched_condition, bool overflowed, int16_t offset);
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void complete_dbcc(bool matched_condition, bool overflowed, int16_t offset);
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@ -16,9 +16,7 @@ namespace InstructionSet {
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namespace M68k {
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namespace M68k {
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#define u_extend16(x) uint32_t(int16_t(x))
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#define u_extend16(x) uint32_t(int16_t(x))
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#define u_extend8(x) uint32_t(int8_t(x))
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#define s_extend16(x) int32_t(int16_t(x))
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#define s_extend16(x) int32_t(int16_t(x))
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#define s_extend8(x) int32_t(int8_t(x))
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template <
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template <
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Model model,
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Model model,
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@ -220,9 +218,7 @@ template <
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status.zero_result_ = dest.l & (1 << (src.l & mask));
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status.zero_result_ = dest.l & (1 << (src.l & mask));
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dest.l &= ~(1 << (src.l & mask));
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dest.l &= ~(1 << (src.l & mask));
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flow_controller.did_bit_op(src.l & mask);
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// // Clearing in the top word requires an extra four cycles.
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// set_next_microcycle_length(HalfCycles(8 + ((src.l & 31) / 16) * 4));
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} break;
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} break;
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case Operation::BCHG: {
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case Operation::BCHG: {
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@ -230,7 +226,7 @@ template <
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status.zero_result_ = dest.l & (1 << (src.l & mask));
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status.zero_result_ = dest.l & (1 << (src.l & mask));
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dest.l ^= 1 << (src.l & mask);
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dest.l ^= 1 << (src.l & mask);
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// set_next_microcycle_length(HalfCycles(4 + (((src.l & 31) / 16) * 4)));
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flow_controller.did_bit_op(src.l & mask);
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} break;
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} break;
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case Operation::BSET: {
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case Operation::BSET: {
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@ -238,15 +234,9 @@ template <
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status.zero_result_ = dest.l & (1 << (src.l & mask));
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status.zero_result_ = dest.l & (1 << (src.l & mask));
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dest.l |= 1 << (src.l & mask);
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dest.l |= 1 << (src.l & mask);
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// set_next_microcycle_length(HalfCycles(4 + (((src.l & 31) / 16) * 4)));
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flow_controller.did_bit_op(src.l & mask);
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} break;
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} break;
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// Bcc: ordinarily evaluates the relevant condition and displacement size and then:
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// if condition is false, schedules bus operations to get past this instruction;
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// otherwise applies the offset and schedules bus operations to refill the prefetch queue.
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//
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// Special case: the condition code is 1, which is ordinarily false. In that case this
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// is the trailing step of a BSR.
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case Operation::Bccb:
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case Operation::Bccb:
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flow_controller.template complete_bcc<int8_t>(
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flow_controller.template complete_bcc<int8_t>(
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status.evaluate_condition(instruction.condition()),
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status.evaluate_condition(instruction.condition()),
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@ -860,9 +850,7 @@ template <
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int shift_count = src.l & 63; \
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int shift_count = src.l & 63; \
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flow_controller.did_shift(shift_count);
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flow_controller.did_shift(shift_count);
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//#define set_flags_b(t) set_flags(dest.b, 0x80, t)
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#define set_flags_w(t) set_flags(src.w, 0x8000, t)
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#define set_flags_w(t) set_flags(src.w, 0x8000, t)
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//#define set_flags_l(t) set_flags(dest.l, 0x80000000, t)
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#define asl(destination, size) {\
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#define asl(destination, size) {\
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decode_shift_count(); \
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decode_shift_count(); \
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@ -1101,9 +1089,7 @@ template <
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#undef set_flags
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#undef set_flags
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#undef decode_shift_count
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#undef decode_shift_count
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//#undef set_flags_b
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#undef set_flags_w
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#undef set_flags_w
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//#undef set_flags_l
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#undef set_neg_zero_overflow
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#undef set_neg_zero_overflow
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#undef set_neg_zero
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#undef set_neg_zero
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@ -1185,9 +1171,7 @@ template <
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#undef add_overflow
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#undef add_overflow
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#undef u_extend16
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#undef u_extend16
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#undef u_extend8
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#undef s_extend16
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#undef s_extend16
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#undef s_extend8
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}
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}
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