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Attempt the shifts and rolls.

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This commit is contained in:
Thomas Harte 2022-05-23 09:29:19 -04:00
parent 1e8adc2bd9
commit c6b3281274
2 changed files with 28 additions and 7 deletions
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4
OSBindings/Mac/Clock SignalTests/68000ComparativeTests.mm
View File

@ -174,7 +174,7 @@ struct TestProcessor: public CPU::MC68000Mk2::BusHandler {
@"jmp_jsr.json",
@"lea.json",
// @"link_unlk.json",
// @"lslr_aslr_roxlr_rolr.json",
@"lslr_aslr_roxlr_rolr.json",
@"move_tofrom_srccr.json",
@"move.json",
@"movem.json",
@ -190,7 +190,7 @@ struct TestProcessor: public CPU::MC68000Mk2::BusHandler {
@"tas.json",
@"tst.json",
]];
// _testSet = [NSSet setWithArray:@[@"MOVE[A] 094d"]];
_testSet = [NSSet setWithArray:@[@"ASL/R e0d0"]];
}
- (void)testAll {

31
Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
View File

@ -161,7 +161,7 @@ enum ExecutionState: int {
MOVEMtoM_finish,
DIVU_DIVS,
MULU_MULS,
Perform_idle_dyamic_Dn,
LEA,
PEA,
TAS,
@ -706,8 +706,8 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
StdCASE(DIVU, perform_state_ = DIVU_DIVS);
StdCASE(DIVS, perform_state_ = DIVU_DIVS);
StdCASE(MULU, perform_state_ = MULU_MULS);
StdCASE(MULS, perform_state_ = MULU_MULS);
StdCASE(MULU, perform_state_ = Perform_idle_dyamic_Dn);
StdCASE(MULS, perform_state_ = Perform_idle_dyamic_Dn);
StdCASE(LEA, {
post_ea_state_ = LEA;
@ -750,6 +750,23 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
StdCASE(RTE, MoveToStateSpecific(RTE));
StdCASE(RTS, MoveToStateSpecific(RTS));
#define ShiftGroup(suffix, state) \
Duplicate(ASL##suffix, ASR##suffix); \
Duplicate(LSL##suffix, ASR##suffix); \
Duplicate(LSR##suffix, ASR##suffix); \
Duplicate(ROL##suffix, ASR##suffix); \
Duplicate(ROR##suffix, ASR##suffix); \
Duplicate(ROXL##suffix, ASR##suffix); \
Duplicate(ROXR##suffix, ASR##suffix); \
StdCASE(ASR##suffix, post_ea_state_ = state );
ShiftGroup(m, Perform_np)
ShiftGroup(b, Perform_idle_dyamic_Dn)
ShiftGroup(w, Perform_idle_dyamic_Dn)
ShiftGroup(l, Perform_idle_dyamic_Dn)
#undef ShiftGroup
default:
assert(false);
}
@ -1955,9 +1972,9 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
MoveToStateSpecific(Decode);
//
// MULU and MULS
// MULU, MULS and shifts
//
BeginState(MULU_MULS):
BeginState(Perform_idle_dyamic_Dn):
Prefetch(); // np
// Perform the instruction.
@ -2192,6 +2209,10 @@ template <typename IntT> void ProcessorBase::did_muls(IntT) {
// TODO: calculate cost.
}
void ProcessorBase::did_shift(int) {
// TODO: calculate cost.
}
template <bool use_current_instruction_pc> void ProcessorBase::raise_exception(int vector) {
// No overt action is taken here; instructions that might throw an exception are required
// to check-in after the fact.