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https://github.com/TomHarte/CLK.git
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Attempt to wire up timer interrupts.
This commit is contained in:
Thomas Harte
parent
6efc41ded7
commit
c6b91559e1
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@ -20,6 +20,11 @@ namespace InstructionSet::ARM {
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/// memory. No hooks are currently provided for applying realistic timing.
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template <Model model, typename MemoryT>
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struct Executor {
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template <typename... Args>
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Executor(Args &&...args) : bus(std::forward<Args...>(args)...) {}
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/// @returns @c true if @c condition implies an appropriate perform call should be made for this instruction,
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/// @c false otherwise.
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bool should_schedule(Condition condition) {
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return registers_.test(condition);
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}
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@ -170,6 +170,29 @@ struct Registers {
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set_pc(uint32_t(type));
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}
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/// Applies an exception of @c type and returns @c true if: (i) it is IRQ or FIQ; (ii) the processor is currently accepting such interrupts.
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/// Otherwise returns @c false.
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template <Exception type>
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bool interrupt() {
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switch(type) {
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case Exception::IRQ:
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if(interrupt_flags_ & ConditionCode::IRQDisable) {
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return false;
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}
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break;
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case Exception::FIQ:
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if(interrupt_flags_ & ConditionCode::FIQDisable) {
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return false;
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}
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break;
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default: return false;
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}
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exception<type>();
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}
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// MARK: - Condition tests.
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/// @returns @c true if @c condition tests as true; @c false otherwise.
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@ -164,7 +164,19 @@ namespace IRQA {
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static constexpr uint8_t SetAlways = 0x80;
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}
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namespace InterruptRequests {
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static constexpr int IRQ = 0x01;
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static constexpr int FIQ = 0x02;
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};
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struct Interrupts {
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int interrupt_mask() const {
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return
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((irq_a_.request() | irq_b_.request()) ? InterruptRequests::IRQ : 0) |
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(fiq_.request() ? InterruptRequests::FIQ : 0);
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}
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bool tick_timers() {
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bool did_change_interrupts = false;
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@ -180,8 +192,8 @@ struct Interrupts {
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counters_[c].value = counters_[c].reload;
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switch(c) {
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case 0: did_change_interrupts |= irq_a_.apply(0x20); break;
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case 1: did_change_interrupts |= irq_a_.apply(0x40); break;
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case 0: did_change_interrupts |= irq_a_.apply(IRQA::Timer0); break;
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case 1: did_change_interrupts |= irq_a_.apply(IRQA::Timer1); break;
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default: break;
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}
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// TODO: events for timers 2 and 3. Also remove some branchyness.
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@ -191,7 +203,7 @@ struct Interrupts {
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return did_change_interrupts;
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}
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bool read(uint32_t address, uint8_t &value) {
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bool read(uint32_t address, uint8_t &value) const {
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const auto target = address & 0x7f;
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logger.error().append("IO controller read from %08x", address);
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switch(target) {
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@ -240,12 +252,12 @@ struct Interrupts {
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return true;
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case 0x14:
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logger.error().append("TODO: IRQ clear write %02x", value);
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// b2: clear IF.
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// b3: clear IR.
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// b4: clear POR.
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// b5: clear TM[0].
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// b6: clear TM[1].
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irq_a_.clear(value & 0x7c);
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return true;
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// Interrupts.
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@ -292,6 +304,9 @@ private:
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status |= value;
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return status & mask;
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}
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void clear(uint8_t bits) {
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status &= ~bits;
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}
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};
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Interrupt irq_a_, irq_b_, fiq_;
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@ -304,7 +319,14 @@ private:
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};
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/// Primarily models the MEMC.
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template <typename IOCWriteDelegateT>
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struct Memory {
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Memory(IOCWriteDelegateT &ioc_write_delegate) : ioc_write_delegate_(ioc_write_delegate) {}
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int interrupt_mask() const {
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return ioc_.interrupt_mask();
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}
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void set_rom(const std::vector<uint8_t> &rom) {
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std::copy(
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rom.begin(),
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@ -321,10 +343,6 @@ struct Memory {
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return false;
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}
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if(address == 0x02000078 || address == 0x02400078) {
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printf("%08x: %08x\n", address, source);
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}
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switch (write_zones_[(address >> 21) & 31]) {
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case Zone::DMAAndMEMC:
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if((address & 0b1110'0000'0000'0000'0000) == 0b1110'0000'0000'0000'0000) {
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@ -365,6 +383,7 @@ struct Memory {
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case Zone::IOControllers:
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ioc_.write(address, source);
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ioc_write_delegate_.did_write_ioc();
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return true;
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case Zone::VideoController:
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@ -470,6 +489,7 @@ struct Memory {
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std::array<uint8_t, 2*1024*1024> rom_;
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Interrupts ioc_;
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Video vidc_;
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IOCWriteDelegateT &ioc_write_delegate_;
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template <typename IntT>
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IntT &physical_ram(uint32_t address) {
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@ -692,7 +712,7 @@ class ConcreteMachine:
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ConcreteMachine(
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const Analyser::Static::Target &target,
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const ROMMachine::ROMFetcher &rom_fetcher
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) {
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) : executor_(*this) {
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set_clock_rate(ClockRate);
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constexpr ROM::Name risc_os = ROM::Name::AcornRISCOS319;
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@ -706,8 +726,11 @@ class ConcreteMachine:
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insert_media(target.media);
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}
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private:
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void did_write_ioc() {
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test_interrupts();
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}
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private:
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// MARK: - ScanProducer.
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void set_scan_target(Outputs::Display::ScanTarget *scan_target) override {
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(void)scan_target;
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@ -716,15 +739,9 @@ class ConcreteMachine:
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return Outputs::Display::ScanStatus();
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}
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std::set<uint32_t> all;
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// MARK: - TimedMachine.
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void run_for(Cycles cycles) override {
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static uint32_t last_pc = 0;
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// static uint32_t last_link = 0;
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// static uint32_t last_r0 = 0;
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// static uint32_t last_r1 = 0;
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// static uint32_t last_r10 = 0;
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auto instructions = cycles.as<int>();
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@ -748,11 +765,9 @@ class ConcreteMachine:
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static bool log = false;
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all.insert(instruction);
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if(executor_.pc() == 0x03802b40) {
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printf("");
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}
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// if(executor_.pc() == 0x03802b40) {
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// printf("");
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// }
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// log |= (executor_.pc() > 0x02000000 && executor_.pc() < 0x02000078);
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// log |= executor_.pc() == 0x03801980;
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// log |= (executor_.pc() > 0x03801000);
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@ -814,12 +829,24 @@ class ConcreteMachine:
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timer_divider_ = TimerTarget;
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if(executor_.bus.tick_timers()) {
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logger.error().append("TODO: Interrupts (or maybe in the main loop?)");
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test_interrupts();
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}
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}
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}
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}
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void test_interrupts() {
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using Exception = InstructionSet::ARM::Registers::Exception;
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const int requests = executor_.bus.interrupt_mask();
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if((requests & InterruptRequests::FIQ) && executor_.registers().interrupt<Exception::FIQ>()) {
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return;
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}
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if(requests & InterruptRequests::IRQ) {
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executor_.registers().interrupt<Exception::IRQ>();
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}
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}
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// MARK: - MediaTarget
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bool insert_media(const Analyser::Static::Media &) override {
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// int c = 0;
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@ -834,7 +861,7 @@ class ConcreteMachine:
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// MARK: - ARM execution
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static constexpr auto arm_model = InstructionSet::ARM::Model::ARMv2;
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InstructionSet::ARM::Executor<arm_model, Memory> executor_;
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InstructionSet::ARM::Executor<arm_model, Memory<ConcreteMachine>> executor_;
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};
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}
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