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Merge pull request #641 from TomHarte/DIVSTiming

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Substantially improves DIVS timing.
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Thomas Harte 2019-08-04 20:46:50 -04:00 committed by GitHub
commit c6cf0e914b
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4 changed files with 683 additions and 549 deletions
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35
Machines/Apple/Macintosh/Macintosh.cpp
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@ -154,25 +154,15 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
using Microcycle = CPU::MC68000::Microcycle;
HalfCycles perform_bus_operation(const Microcycle &cycle, int is_supervisor) {
HalfCycles delay(0);
// Grab the word-precision address being accessed.
uint32_t word_address = 0;
// Take a sneak peak and add a delay if this is a RAM access that would overlap with video.
if(cycle.data_select_active()) {
word_address = cycle.active_operation_word_address();
if(memory_map_[word_address >> 18] == BusDevice::RAM && ram_subcycle_ < 4) {
delay = HalfCycles(4 - ram_subcycle_);
}
}
forceinline HalfCycles perform_bus_operation(const Microcycle &cycle, int is_supervisor) {
// Advance time.
advance_time(cycle.length + delay);
advance_time(cycle.length);
// A null cycle leaves nothing else to do.
if(!(cycle.operation & (Microcycle::NewAddress | Microcycle::SameAddress))) return delay;
if(!(cycle.operation & (Microcycle::NewAddress | Microcycle::SameAddress))) return HalfCycles(0);
// Grab the value on the address bus, at word precision.
uint32_t word_address = cycle.active_operation_word_address();
// Everything above E0 0000 is signalled as being on the peripheral bus.
mc68000_.set_is_peripheral_address(word_address >= 0x700000);
@ -185,9 +175,11 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
// having set VPA above deals with those given that the generated address
// for interrupt acknowledge cycles always has all bits set except the
// lowest explicit address lines.
if(!cycle.data_select_active() || (cycle.operation & Microcycle::InterruptAcknowledge)) return delay;
if(!cycle.data_select_active() || (cycle.operation & Microcycle::InterruptAcknowledge)) return HalfCycles(0);
// Grab the word-precision address being accessed.
uint16_t *memory_base = nullptr;
HalfCycles delay;
switch(memory_map_[word_address >> 18]) {
default: assert(false);
@ -289,6 +281,15 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
memory_base = ram_;
word_address &= ram_mask_;
// Apply a delay due to video contention if applicable; technically this is
// incorrectly placed — strictly speaking here I'm extending the part of the
// bus cycle after DTACK rather than delaying DTACK. But it adds up to the
// same thing.
if(ram_subcycle_ < 4) {
delay = HalfCycles(4 - ram_subcycle_);
advance_time(delay);
}
} break;
case BusDevice::ROM: {

3
OSBindings/Mac/Clock Signal.xcodeproj/project.xcworkspace/contents.xcworkspacedata generated
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@ -1,9 +1,6 @@
<?xml version="1.0" encoding="UTF-8"?>
<Workspace
version = "1.0">
<FileRef
location = "group:/Users/thomasharte/Projects/CLK/OSBindings/Mac/Clock SignalTests/68000ArithmeticTests.mm">
</FileRef>
<FileRef
location = "self:Clock Signal.xcodeproj">
</FileRef>

1143
OSBindings/Mac/Clock SignalTests/68000ArithmeticTests.mm
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File diff suppressed because it is too large Load Diff

51
Processors/68000/Implementation/68000Implementation.hpp
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@ -1049,51 +1049,56 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
break;
}
int32_t dividend = int32_t(destination()->full);
int32_t divisor = s_extend16(source()->halves.low.full);
const int64_t quotient = int64_t(dividend) / int64_t(divisor);
const int32_t signed_dividend = int32_t(destination()->full);
const int32_t signed_divisor = s_extend16(source()->halves.low.full);
const auto result_sign =
( (0 <= signed_dividend) - (signed_dividend < 0) ) *
( (0 <= signed_divisor) - (signed_divisor < 0) );
const uint32_t dividend = uint32_t(abs(signed_dividend));
const uint32_t divisor = uint32_t(abs(signed_divisor));
int cycles_expended = 12; // Covers the nn nnn n to get beyond the sign test.
if(dividend < 0) {
if(signed_dividend < 0) {
cycles_expended += 2; // An additional microycle applies if the dividend is negative.
}
// Check for overflow. If it exists, work here is already done.
if(quotient > 32767 || quotient < -32768) {
const auto quotient = dividend / divisor;
if(quotient > 32767) {
overflow_flag_ = 1;
set_next_microcycle_length(HalfCycles(3*2*2));
set_next_microcycle_length(HalfCycles(6*2*2));
// These are officially undefined for results that overflow, so the below is a guess.
zero_result_ = decltype(zero_result_)(divisor & 0xffff);
zero_result_ = decltype(zero_result_)(dividend);
negative_flag_ = zero_result_ & 0x8000;
break;
}
zero_result_ = decltype(zero_result_)(quotient);
const uint16_t remainder = uint16_t(signed_dividend % signed_divisor);
const int signed_quotient = result_sign*int(quotient);
destination()->halves.high.full = remainder;
destination()->halves.low.full = uint16_t(signed_quotient);
zero_result_ = decltype(zero_result_)(signed_quotient);
negative_flag_ = zero_result_ & 0x8000;
overflow_flag_ = 0;
// TODO: check sign rules here; am I necessarily giving the remainder the correct sign?
// (and, if not, am I counting it in the correct direction?)
const uint16_t remainder = uint16_t(dividend % divisor);
destination()->halves.high.full = remainder;
destination()->halves.low.full = uint16_t(quotient);
// Algorithm here: there is a fixed three-microcycle cost per bit set
// in the unsigned quotient; there is an additional microcycle for
// every bit that is set. Also, since the possibility of overflow
// was already dealt with, it's now a smaller number.
int positive_quotient_bits = int(abs(quotient)) & 0xfffe;
// Algorithm here: there is a fixed cost per unset bit
// in the first 15 bits of the unsigned quotient.
auto positive_quotient_bits = ~quotient & 0xfffe;
convert_to_bit_count_16(positive_quotient_bits);
cycles_expended += 2 * positive_quotient_bits;
// There's then no way to terminate the loop that isn't at least six cycles long.
cycles_expended += 6;
// There's then no way to terminate the loop that isn't at least ten cycles long;
// there's also a fixed overhead per bit. The two together add up to the 104 below.
cycles_expended += 104;
if(divisor < 0) {
// This picks up at 'No more bits' in yacht.txt's diagram.
if(signed_divisor < 0) {
cycles_expended += 2;
} else if(dividend < 0) {
} else if(signed_dividend < 0) {
cycles_expended += 4;
}
set_next_microcycle_length(HalfCycles(cycles_expended * 2));