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Corrects CMPI and documentation; implements JMP.
This commit is contained in:
Thomas Harte
parent
cb240cd32a
commit
c6f977ed4b
@ -196,6 +196,11 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
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overflow_flag_ = (source ^ destination) & (destination ^ result) & 0x80000000;
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} break;
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// JMP: copies the source to the program counter.
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case Operation::JMP:
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program_counter_.full = active_program_->source->full;
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break;
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/*
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MOVE.b, MOVE.l and MOVE.w: move the least significant byte or word, or the entire long word,
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and set negative, zero, overflow and carry as appropriate.
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@ -364,6 +369,19 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
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}
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break;
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case int(MicroOp::Action::CalcD16PC) | MicroOp::SourceMask:
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effective_address_[0] = int16_t(prefetch_queue_.halves.low.full) + program_counter_.full;
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break;
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case int(MicroOp::Action::CalcD16PC) | MicroOp::DestinationMask:
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effective_address_[1] = int16_t(prefetch_queue_.halves.low.full) + program_counter_.full;
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break;
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case int(MicroOp::Action::CalcD16PC) | MicroOp::SourceMask | MicroOp::DestinationMask:
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effective_address_[0] = int16_t(prefetch_queue_.halves.high.full) + program_counter_.full;
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effective_address_[1] = int16_t(prefetch_queue_.halves.low.full) + program_counter_.full;
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break;
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case int(MicroOp::Action::CalcD16An) | MicroOp::SourceMask:
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effective_address_[0] = int16_t(prefetch_queue_.halves.low.full) + active_program_->source->full;
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break;
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@ -422,19 +440,32 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
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case int(MicroOp::Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask:
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// Assumption: this will be assembling right at the start of the instruction.
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bus_data_[0] = prefetch_queue_.halves.low.full;
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source_bus_data_[0] = prefetch_queue_.halves.low.full;
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break;
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case int(MicroOp::Action::AssembleWordDataFromPrefetch) | MicroOp::DestinationMask:
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bus_data_[1] = prefetch_queue_.halves.low.full;
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destination_bus_data_[0] = prefetch_queue_.halves.low.full;
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break;
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case int(MicroOp::Action::AssembleLongWordDataFromPrefetch) | MicroOp::SourceMask:
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bus_data_[0] = prefetch_queue_.full;
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source_bus_data_[0] = prefetch_queue_.full;
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break;
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case int(MicroOp::Action::AssembleLongWordDataFromPrefetch) | MicroOp::DestinationMask:
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bus_data_[1] = prefetch_queue_.full;
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destination_bus_data_[0] = prefetch_queue_.full;
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break;
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case int(MicroOp::Action::CopyToEffectiveAddress) | MicroOp::SourceMask:
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effective_address_[0] = *active_program_->source;
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break;
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case int(MicroOp::Action::CopyToEffectiveAddress) | MicroOp::DestinationMask:
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effective_address_[1] = *active_program_->destination;
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break;
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case int(MicroOp::Action::CopyToEffectiveAddress) | MicroOp::SourceMask | MicroOp::DestinationMask:
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effective_address_[0] = *active_program_->source;
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effective_address_[1] = *active_program_->destination;
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break;
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}
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@ -47,26 +47,35 @@ struct ProcessorStorageConstructor {
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during this program. This should follow the same general pattern as
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those in yacht.txt; full description below.
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@discussion
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The access pattern is defined, as in yacht.txt, to be a string consisting
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of the following discrete bus actions. Spaces are ignored.
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@param addresses A vector of the addresses to place on the bus coincident
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with those acess steps that require them.
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* n: no operation; data bus is not used;
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* -: idle state; data bus is not used but is also not available;
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* p: program fetch; reads from the PC and adds two to it;
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* W: write MSW of something onto the bus;
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* w: write LSW of something onto the bus;
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* R: read MSW of something from the bus;
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* r: read LSW of soemthing from the bus;
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* S: push the MSW of something onto the stack;
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* s: push the LSW of something onto the stack;
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* U: pop the MSW of something from the stack;
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* u: pop the LSW of something from the stack;
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* V: fetch a vector's MSW;
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* v: fetch a vector's LSW;
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@param read_full_words @c true to indicate that read and write operations are
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selecting a full word; @c false to signal byte accesses only.
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@discussion
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The access pattern is defined to correlate closely to that in yacht.txt; it is
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a space-separated sequence of the following actions:
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* n: no operation for four cycles; data bus is not used;
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* nn: no operation for eight cycles; data bus is not used;
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* np: program fetch; reads from the PC and adds two to it, advancing the prefetch queue;
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* nW: write MSW of something onto the bus;
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* nw: write LSW of something onto the bus;
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* nR: read MSW of something from the bus into the source latch;
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* nr: read LSW of soemthing from the bus into the source latch;
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* nRd: read MSW of something from the bus into the destination latch;
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* nrd: read LSW of soemthing from the bus into the destination latch;
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* nS: push the MSW of something onto the stack;
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* ns: push the LSW of something onto the stack;
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* nU: pop the MSW of something from the stack;
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* nu: pop the LSW of something from the stack;
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* nV: fetch a vector's MSW;
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* nv: fetch a vector's LSW;
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* i: acquire interrupt vector in an IACK cycle;
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* F: fetch the SSPs MSW;
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* f: fetch the SSP's LSW.
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* nF: fetch the SSPs MSW;
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* nf: fetch the SSP's LSW;
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* _: hold the reset line active for the usual period.
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Quite a lot of that is duplicative, implying both something about internal
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state and something about what's observable on the bus, but it's helpful to
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@ -82,8 +91,6 @@ struct ProcessorStorageConstructor {
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*/
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size_t assemble_program(std::string access_pattern, const std::vector<uint32_t *> &addresses = {}, bool read_full_words = true) {
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auto address_iterator = addresses.begin();
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RegisterPair32 *scratch_data_read = storage_.bus_data_;
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RegisterPair32 *scratch_data_write = storage_.bus_data_;
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using Action = BusStep::Action;
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std::vector<BusStep> steps;
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@ -162,14 +169,15 @@ struct ProcessorStorageConstructor {
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}
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// A standard read or write.
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if(token == "nR" || token == "nr" || token == "nW" || token == "nw") {
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const bool is_read = tolower(access_pattern[1]) == 'r';
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RegisterPair32 **scratch_data = is_read ? &scratch_data_read : &scratch_data_write;
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if(token == "nR" || token == "nr" || token == "nW" || token == "nw" || token == "nRd" || token == "nrd") {
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const bool is_read = tolower(token[1]) == 'r';
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const bool use_source_storage = is_read && token.size() != 3;
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RegisterPair32 *scratch_data = use_source_storage ? &storage_.source_bus_data_[0] : &storage_.destination_bus_data_[0];
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step.microcycle.length = HalfCycles(5);
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step.microcycle.operation = Microcycle::NewAddress | (is_read ? Microcycle::Read : 0);
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step.microcycle.address = *address_iterator;
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step.microcycle.value = isupper(token[1]) ? &(*scratch_data)->halves.high : &(*scratch_data)->halves.low;
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step.microcycle.value = isupper(token[1]) ? &scratch_data->halves.high : &scratch_data->halves.low;
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steps.push_back(step);
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step.microcycle.length = HalfCycles(3);
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@ -182,8 +190,7 @@ struct ProcessorStorageConstructor {
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}
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steps.push_back(step);
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if(!isupper(access_pattern[1])) {
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++(*scratch_data);
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if(!isupper(token[1])) {
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++address_iterator;
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}
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@ -241,7 +248,8 @@ struct ProcessorStorageConstructor {
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Bcc, // twelve lowest bits are ignored, only a PerformAction is scheduled
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LEA, // decodes register, mode, register
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MOVEq, // decodes just a destination register
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RESET, // no further decoding applied
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RESET, // no further decoding applied, performs reset cycle
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JMP, // six lowest bits are [mode, register], decoding to JMP
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};
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using Operation = ProcessorStorage::Operation;
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@ -294,6 +302,8 @@ struct ProcessorStorageConstructor {
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{0xf100, 0x7000, Operation::MOVEq, Decoder::MOVEq}, // 4-134 (p238)
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{0xffff, 0x4e70, Operation::None, Decoder::RESET}, // 6-83 (p537)
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{0xffc0, 0x4ec0, Operation::JMP, Decoder::JMP}, // 4-108 (p212)
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};
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std::vector<size_t> micro_op_pointers(65536, std::numeric_limits<size_t>::max());
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@ -335,8 +345,8 @@ struct ProcessorStorageConstructor {
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const int source = instruction & 7;
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if(instruction & 8) {
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storage_.instructions[instruction].source = &storage_.bus_data_[0];
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storage_.instructions[instruction].destination = &storage_.bus_data_[1];
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storage_.instructions[instruction].source = &storage_.source_bus_data_[0];
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storage_.instructions[instruction].destination = &storage_.destination_bus_data_[0];
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op( int(Action::Decrement1) | MicroOp::SourceMask | MicroOp::DestinationMask,
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seq("n nr nr np nw", { &storage_.address_[source].full, &storage_.address_[destination].full, &storage_.address_[destination].full }, false));
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@ -355,7 +365,7 @@ struct ProcessorStorageConstructor {
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const auto destination_mode = source_mode;
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const auto destination_register = source_register;
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storage_.instructions[instruction].source = &storage_.bus_data_[0];
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storage_.instructions[instruction].source = &storage_.source_bus_data_[0];
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storage_.instructions[instruction].set_destination(storage_, destination_mode, destination_register);
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const bool is_byte_access = mapping.operation == Operation::CMPb;
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@ -375,7 +385,7 @@ struct ProcessorStorageConstructor {
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case 0x002: // CMPI.bw #, (An)
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case 0x003: // CMPI.bw #, (An)+
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op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np nr np", { &storage_.address_[destination_register].full }, !is_byte_access));
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op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np nrd np", { &storage_.address_[destination_register].full }, !is_byte_access));
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if(mode == 0x3) {
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op(int(is_byte_access ? Action::Increment1 : Action::Increment2) | MicroOp::DestinationMask);
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}
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@ -385,7 +395,7 @@ struct ProcessorStorageConstructor {
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case 0x102: // CMPI.l #, (An)
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case 0x103: // CMPI.l #, (An)+
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op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask, seq("np"));
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op(int(Action::AssembleLongWordDataFromPrefetch) | MicroOp::SourceMask, seq("np nR nr np", { &storage_.effective_address_[1].full }));
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op(int(Action::AssembleLongWordDataFromPrefetch) | MicroOp::SourceMask, seq("np nRd nrd np", { &storage_.effective_address_[1].full }));
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if(mode == 0x103) {
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op(int(Action::Increment4) | MicroOp::DestinationMask);
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}
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@ -394,14 +404,14 @@ struct ProcessorStorageConstructor {
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case 0x004: // CMPI.bw #, -(An)
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op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np n"));
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op(int(is_byte_access ? Action::Decrement1 : Action::Decrement1) | MicroOp::DestinationMask, seq("nr np", { &storage_.address_[destination_register].full }));
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op(int(is_byte_access ? Action::Decrement1 : Action::Decrement1) | MicroOp::DestinationMask, seq("nrd np", { &storage_.address_[destination_register].full }));
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op(Action::PerformOperation);
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break;
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case 0x104: // CMPI.l #, -(An)
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op(int(Action::Decrement4) | MicroOp::DestinationMask, seq("np"));
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op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np n"));
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op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask, seq("nR nr np", { &storage_.effective_address_[1].full }));
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op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask, seq("nRd nrd np", { &storage_.effective_address_[1].full }));
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op(Action::PerformOperation);
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break;
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@ -411,7 +421,7 @@ struct ProcessorStorageConstructor {
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case 0x006: // CMPI.bw #, (d8, An, Xn)
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op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np"));
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op( calc_action_for_mode(mode) | MicroOp::DestinationMask,
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seq(pseq("nr np", mode), { &storage_.effective_address_[1].full }, !is_byte_access));
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seq(pseq("nrd np", mode), { &storage_.effective_address_[1].full }, !is_byte_access));
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op(Action::PerformOperation);
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break;
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@ -422,33 +432,33 @@ struct ProcessorStorageConstructor {
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op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask, seq("np"));
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op(int(Action::AssembleLongWordDataFromPrefetch) | MicroOp::SourceMask, seq("np"));
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op( calc_action_for_mode(mode) | MicroOp::DestinationMask,
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seq(pseq("np nR nr np", mode), { &storage_.effective_address_[1].full }));
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seq(pseq("np nRd nrd np", mode), { &storage_.effective_address_[1].full }));
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op(Action::PerformOperation);
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break;
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case 0x010: // CMPI.bw #, (xxx).w
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op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np"));
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op(int(Action::AssembleWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("np nr np", { &storage_.effective_address_[1].full }, !is_byte_access));
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op(int(Action::AssembleWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("np nrd np", { &storage_.effective_address_[1].full }, !is_byte_access));
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op(Action::PerformOperation);
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break;
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case 0x110: // CMPI.l #, (xxx).w
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op(Action::None, seq("np"));
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op(int(Action::AssembleLongWordDataFromPrefetch) | MicroOp::SourceMask, seq("np np"));
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op(int(Action::AssembleWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("nR nr np", { &storage_.effective_address_[1].full }));
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op(int(Action::AssembleWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("nRd nrd np", { &storage_.effective_address_[1].full }));
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op(Action::PerformOperation);
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break;
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case 0x011: // CMPI.bw #, (xxx).l
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op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np np"));
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op(int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("np nr np", { &storage_.effective_address_[1].full }, !is_byte_access));
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op(int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("np nrd np", { &storage_.effective_address_[1].full }, !is_byte_access));
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op(Action::PerformOperation);
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break;
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case 0x111: // CMPI.l #, (xxx).l
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op(Action::None, seq("np"));
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op(int(Action::AssembleLongWordDataFromPrefetch) | MicroOp::SourceMask, seq("np np"));
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op(int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("np nR nr np", { &storage_.effective_address_[1].full }));
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op(int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("np nRd nrd np", { &storage_.effective_address_[1].full }));
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op(Action::PerformOperation);
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break;
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@ -456,6 +466,41 @@ struct ProcessorStorageConstructor {
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}
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} break;
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case Decoder::JMP: {
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storage_.instructions[instruction].source = &storage_.effective_address_[0];
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const int mode = combined_mode(source_mode, source_register);
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switch(mode) {
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default: continue;
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case 0x02: // JMP (An)
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storage_.instructions[instruction].source = &storage_.address_[source_register];
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op(Action::PerformOperation, seq("np np"));
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break;
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case 0x12: // JMP (d16, PC)
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case 0x05: // JMP (d16, An)
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op(calc_action_for_mode(mode) | MicroOp::SourceMask, seq("n np np", { &storage_.effective_address_[0].full }));
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op(Action::PerformOperation);
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break;
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case 0x13: // JMP (d8, PC, Xn)
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case 0x06: // JMP (d8, An, Xn)
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op(calc_action_for_mode(mode) | MicroOp::SourceMask, seq("n nn np np", { &storage_.effective_address_[0].full }));
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op(Action::PerformOperation);
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break;
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case 0x10: // JMP (xxx).W
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op(int(MicroOp::Action::AssembleWordAddressFromPrefetch) | MicroOp::SourceMask);
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op(Action::PerformOperation, seq("n np np"));
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break;
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case 0x11: // JMP (xxx).L
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op(Action::None, seq("np"));
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op(int(MicroOp::Action::AssembleLongWordAddressFromPrefetch) | MicroOp::SourceMask);
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op(Action::PerformOperation, seq("np np"));
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break;
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}
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} break;
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case Decoder::LEA: {
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const int destination_register = (instruction >> 9) & 7;
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storage_.instructions[instruction].destination = &storage_.address_[destination_register];
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@ -581,7 +626,7 @@ struct ProcessorStorageConstructor {
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break;
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default: // (An), (An)+, -(An), (d16, An), (d8, An Xn), (xxx).W, (xxx).L
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storage_.instructions[instruction].source = &storage_.bus_data_[0];
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storage_.instructions[instruction].source = &storage_.source_bus_data_[0];
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break;
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}
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@ -595,7 +640,7 @@ struct ProcessorStorageConstructor {
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break;
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default: // (An), (An)+, -(An), (d16, An), (d8, An Xn), (xxx).W, (xxx).L
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storage_.instructions[instruction].destination = &storage_.bus_data_[1];
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storage_.instructions[instruction].destination = &storage_.destination_bus_data_[0];
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break;
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}
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@ -1126,6 +1171,7 @@ struct ProcessorStorageConstructor {
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} break;
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case Decoder::RESET:
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storage_.instructions[instruction].requires_supervisor = true;
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op(Action::None, seq("nn _ np"));
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break;
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@ -37,7 +37,8 @@ class ProcessorStorage {
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// Generic sources and targets for memory operations;
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// by convention: [0] = source, [1] = destination.
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RegisterPair32 effective_address_[2];
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RegisterPair32 bus_data_[2];
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RegisterPair32 source_bus_data_[1];
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RegisterPair32 destination_bus_data_[1];
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HalfCycles half_cycles_left_to_run_;
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|
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@ -53,7 +54,7 @@ class ProcessorStorage {
|
||||
|
||||
CMPb, CMPw, CMPl,
|
||||
|
||||
BRA, Bcc,
|
||||
BRA, Bcc, JMP
|
||||
};
|
||||
|
||||
/*!
|
||||
@ -211,7 +212,7 @@ class ProcessorStorage {
|
||||
switch(mode) {
|
||||
case 0: source = &storage.data_[reg]; break;
|
||||
case 1: source = &storage.address_[reg]; break;
|
||||
default: source = &storage.bus_data_[0]; break;
|
||||
default: source = &storage.source_bus_data_[0]; break;
|
||||
}
|
||||
}
|
||||
|
||||
@ -219,7 +220,7 @@ class ProcessorStorage {
|
||||
switch(mode) {
|
||||
case 0: destination = &storage.data_[reg]; break;
|
||||
case 1: destination = &storage.address_[reg]; break;
|
||||
default: destination = &storage.bus_data_[1]; break;
|
||||
default: destination = &storage.destination_bus_data_[0]; break;
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user