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https://github.com/TomHarte/CLK.git
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Completes import of LSL tests and fixes various LSL issues.
Including LSL (xxx).w actually being LSR, and the carry flag generally being questionable.
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c447655047
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@ -1736,6 +1736,36 @@ class CPU::MC68000::ProcessorStorageTests {
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XCTAssertEqual(72, _machine->get_cycle_count());
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XCTAssertEqual(72, _machine->get_cycle_count());
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}
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}
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- (void)testLSLl_Imm {
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_machine->set_program({
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0xe189 // LSL.l #8, D1
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});
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auto state = _machine->get_processor_state();
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state.data[1] = 0xce3dd567;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(state.data[1], 0x3dd56700);
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XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
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XCTAssertEqual(24, _machine->get_cycle_count());
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}
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- (void)testLSL_XXXw {
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_machine->set_program({
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0xe3f8, 0x3000 // LSL.l ($3000).w
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});
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*_machine->ram_at(0x3000) = 0x8ccc;
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_machine->run_for_instructions(1);
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const auto state = _machine->get_processor_state();
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XCTAssertEqual(*_machine->ram_at(0x3000), 0x1998);
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XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Extend);
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XCTAssertEqual(16, _machine->get_cycle_count());
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}
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// MARK: MOVEM
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// MARK: MOVEM
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- (void)testMOVEM {
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- (void)testMOVEM {
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@ -1558,7 +1558,7 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
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carry_flag_ = 0; \
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carry_flag_ = 0; \
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} else { \
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} else { \
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destination = (shift_count < size) ? decltype(destination)(value << shift_count) : 0; \
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destination = (shift_count < size) ? decltype(destination)(value << shift_count) : 0; \
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extend_flag_ = carry_flag_ = decltype(carry_flag_)(value) & decltype(carry_flag_)( (1 << (size - 1)) >> (shift_count - 1) ); \
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extend_flag_ = carry_flag_ = decltype(carry_flag_)(value) & decltype(carry_flag_)( (1u << (size - 1)) >> (shift_count - 1) ); \
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} \
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} \
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\
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\
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set_neg_zero_overflow(destination, 1 << (size - 1)); \
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set_neg_zero_overflow(destination, 1 << (size - 1)); \
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@ -1623,8 +1623,8 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
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case Operation::LSLm: {
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case Operation::LSLm: {
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const auto value = active_program_->destination->halves.low.full;
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const auto value = active_program_->destination->halves.low.full;
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active_program_->destination->halves.low.full = value >> 1;
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active_program_->destination->halves.low.full = uint16_t(value << 1);
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extend_flag_ = carry_flag_ = value & 1;
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extend_flag_ = carry_flag_ = value & 0x8000;
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set_neg_zero_overflow(active_program_->destination->halves.low.full, 0x8000);
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set_neg_zero_overflow(active_program_->destination->halves.low.full, 0x8000);
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} break;
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} break;
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case Operation::LSLb: lsl(active_program_->destination->halves.low.halves.low, 8); break;
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case Operation::LSLb: lsl(active_program_->destination->halves.low.halves.low, 8); break;
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