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Fix CalcEA timing; make MOVEfromSR a read-modify-write.

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This commit is contained in:
Thomas Harte
2022-05-27 10:32:28 -04:00
parent 5f030edea4
commit c97245e626
2 changed files with 17 additions and 16 deletions
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5
InstructionSets/M68k/Implementation/InstructionOperandFlags.hpp
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@@ -45,7 +45,7 @@ template <Model model, Operation t_operation> constexpr uint8_t operand_flags(Op
// //
// Single-operand write. // Single-operand write.
// //
case Operation::MOVEfromSR: case Operation::MOVEfromUSP: case Operation::MOVEfromUSP:
return StoreOp1; return StoreOp1;
// //
@@ -66,8 +66,9 @@ template <Model model, Operation t_operation> constexpr uint8_t operand_flags(Op
return FetchOp1 | StoreOp1; return FetchOp1 | StoreOp1;
// //
// CLR, which is model-dependent. // CLR and MOVE SR, which are model-dependent.
// //
case Operation::MOVEfromSR:
case Operation::CLRb: case Operation::CLRw: case Operation::CLRl: case Operation::CLRb: case Operation::CLRw: case Operation::CLRl:
if constexpr (model == Model::M68000) { if constexpr (model == Model::M68000) {
return FetchOp1 | StoreOp1; return FetchOp1 | StoreOp1;

28
Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
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@@ -86,16 +86,16 @@ enum ExecutionState: int {
FetchAbsoluteLong_l, FetchAbsoluteLong_l,
FetchImmediateData_l, FetchImmediateData_l,
CalcEffectiveAddress, CalcEffectiveAddress, // -
CalcAddressRegisterIndirect, CalcAddressRegisterIndirect, // -
CalcAddressRegisterIndirectWithPostincrement, CalcAddressRegisterIndirectWithPostincrement, // -
CalcAddressRegisterIndirectWithPredecrement, CalcAddressRegisterIndirectWithPredecrement, // -
CalcAddressRegisterIndirectWithDisplacement, CalcAddressRegisterIndirectWithDisplacement, // np
CalcAddressRegisterIndirectWithIndex8bitDisplacement, CalcAddressRegisterIndirectWithIndex8bitDisplacement, // n np n
CalcProgramCounterIndirectWithDisplacement, CalcProgramCounterIndirectWithDisplacement, // np
CalcProgramCounterIndirectWithIndex8bitDisplacement, CalcProgramCounterIndirectWithIndex8bitDisplacement, // n np n
CalcAbsoluteShort, CalcAbsoluteShort, // np
CalcAbsoluteLong, CalcAbsoluteLong, // np np
// Various forms of perform; each of these will // Various forms of perform; each of these will
// perform the current instruction, then do the // perform the current instruction, then do the
@@ -941,14 +941,12 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
Duplicate(MOVEtoCCR, MOVEtoSR); Duplicate(MOVEtoCCR, MOVEtoSR);
StdCASE(MOVEtoSR, perform_state_ = MOVEtoCCRSR); StdCASE(MOVEtoSR, perform_state_ = MOVEtoCCRSR);
StdCASE(MOVEfromSR, { StdCASE(MOVEfromSR, {
if(instruction_.mode(0) == Mode::DataRegisterDirect) { if(instruction_.mode(0) == Mode::DataRegisterDirect) {
post_ea_state_ = Perform_np_n; perform_state_ = Perform_np_n;
} else { } else {
post_ea_state_ = Perform_np; perform_state_ = Perform_np;
} }
MoveToStateSpecific(CalcEffectiveAddress);
}); });
SpecialCASE(RTR); SpecialCASE(RTR);
@@ -1322,6 +1320,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
BeginState(CalcAddressRegisterIndirectWithIndex8bitDisplacement): BeginState(CalcAddressRegisterIndirectWithIndex8bitDisplacement):
effective_address_[next_operand_].l = d8Xn(registers_[8 + instruction_.reg(next_operand_)].l); effective_address_[next_operand_].l = d8Xn(registers_[8 + instruction_.reg(next_operand_)].l);
IdleBus(1); // n
Prefetch(); // np Prefetch(); // np
IdleBus(1); // n IdleBus(1); // n
MoveToStateDynamic(post_ea_state_); MoveToStateDynamic(post_ea_state_);
@@ -1357,6 +1356,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
BeginState(CalcProgramCounterIndirectWithIndex8bitDisplacement): BeginState(CalcProgramCounterIndirectWithIndex8bitDisplacement):
effective_address_[next_operand_].l = d8Xn(program_counter_.l - 2); effective_address_[next_operand_].l = d8Xn(program_counter_.l - 2);
IdleBus(1); // n
Prefetch(); // np Prefetch(); // np
IdleBus(1); // n IdleBus(1); // n
MoveToStateDynamic(post_ea_state_); MoveToStateDynamic(post_ea_state_);