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Fixed: Scc is a byte operation.
It was, until now, post-incrementing and pre-decrementing registers other than A7 incorrectly.
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68a3e5a739
commit
ca83431e54
@ -2277,10 +2277,14 @@ struct ProcessorStorageConstructor {
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} else {
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} else {
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// This is an Scc.
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// This is an Scc.
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// Scc is inexplicably a read-modify-write operation.
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// Scc is implemented on the 68000 a read-modify-write operation.
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storage_.instructions[instruction].set_source(storage_, ea_mode, ea_register);
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storage_.instructions[instruction].set_source(storage_, ea_mode, ea_register);
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storage_.instructions[instruction].set_destination(storage_, ea_mode, ea_register);
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storage_.instructions[instruction].set_destination(storage_, ea_mode, ea_register);
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// Scc is always a byte operation.
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is_byte_access = true;
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is_long_word_access = false;
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const int mode = combined_mode(ea_mode, ea_register);
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const int mode = combined_mode(ea_mode, ea_register);
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switch(mode) {
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switch(mode) {
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default: continue;
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default: continue;
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