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Switches to a more explicit tokeniser, to allow for greater flexibility momentarily.
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Thomas Harte
parent
bc6349f823
commit
cb240cd32a
@ -9,6 +9,7 @@
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#include "../68000.hpp"
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#include <algorithm>
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#include <sstream>
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namespace CPU {
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namespace MC68000 {
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@ -35,7 +36,7 @@ struct ProcessorStorageConstructor {
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return (mode == 7) ? (0x10 | reg) : mode;
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}
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#define pseq(x, m) ((((m)&0xff) == 0x06) || (((m)&0xff) == 0x13) ? "n" x : x)
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#define pseq(x, m) ((((m)&0xff) == 0x06) || (((m)&0xff) == 0x13) ? "n " x : x)
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/*!
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Installs BusSteps that implement the described program into the relevant
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@ -79,129 +80,118 @@ struct ProcessorStorageConstructor {
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The user should fill in the steps necessary to get data into or extract
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data from those.
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*/
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size_t assemble_program(const char *access_pattern, const std::vector<uint32_t *> &addresses = {}, bool read_full_words = true) {
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size_t assemble_program(std::string access_pattern, const std::vector<uint32_t *> &addresses = {}, bool read_full_words = true) {
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auto address_iterator = addresses.begin();
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RegisterPair32 *scratch_data_read = storage_.bus_data_;
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RegisterPair32 *scratch_data_write = storage_.bus_data_;
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using Action = BusStep::Action;
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std::vector<BusStep> steps;
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std::stringstream stream(access_pattern);
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// Parse the access pattern to build microcycles.
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while(*access_pattern) {
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// Tokenise the access pattern by splitting on spaces.
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std::string token;
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while(stream >> token) {
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ProcessorBase::BusStep step;
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switch(*access_pattern) {
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case '\t': case ' ': // White space acts as a no-op; it's for clarity only.
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++access_pattern;
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break;
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case 'n': // This might be a plain NOP cycle, in which some internal calculation occurs,
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// or it might pair off with something afterwards.
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switch(access_pattern[1]) {
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default: // This is probably a pure NOP; if what comes after this 'n' isn't actually
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// valid, it should be caught in the outer switch the next time around the loop.
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steps.push_back(step);
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++access_pattern;
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break;
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case '-': // This is two NOPs in a row.
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steps.push_back(step);
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steps.push_back(step);
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access_pattern += 2;
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break;
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case 'F': // Fetch SSP MSW.
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case 'f': // Fetch SSP LSW.
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step.microcycle.length = HalfCycles(5);
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step.microcycle.operation = Microcycle::NewAddress | Microcycle::Read | Microcycle::IsProgram; // IsProgram is a guess.
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step.microcycle.address = &storage_.effective_address_[0].full;
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step.microcycle.value = isupper(access_pattern[1]) ? &storage_.stack_pointers_[1].halves.high : &storage_.stack_pointers_[1].halves.low;
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steps.push_back(step);
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step.microcycle.length = HalfCycles(3);
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step.microcycle.operation = Microcycle::SelectWord | Microcycle::Read | Microcycle::IsProgram;
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step.action = Action::IncrementEffectiveAddress0;
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steps.push_back(step);
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access_pattern += 2;
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break;
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case 'V': // Fetch exception vector low.
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case 'v': // Fetch exception vector high.
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step.microcycle.length = HalfCycles(5);
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step.microcycle.operation = Microcycle::NewAddress | Microcycle::Read | Microcycle::IsProgram; // IsProgram is a guess.
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step.microcycle.address = &storage_.effective_address_[0].full;
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step.microcycle.value = isupper(access_pattern[1]) ? &storage_.program_counter_.halves.high : &storage_.program_counter_.halves.low;
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steps.push_back(step);
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step.microcycle.length = HalfCycles(3);
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step.microcycle.operation |= Microcycle::SelectWord | Microcycle::Read | Microcycle::IsProgram;
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step.action = Action::IncrementEffectiveAddress0;
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steps.push_back(step);
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access_pattern += 2;
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break;
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case 'p': // Fetch from the program counter into the prefetch queue.
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step.microcycle.length = HalfCycles(5);
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step.microcycle.operation = Microcycle::NewAddress | Microcycle::Read | Microcycle::IsProgram;
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step.microcycle.address = &storage_.program_counter_.full;
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step.microcycle.value = &storage_.prefetch_queue_.halves.low;
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step.action = Action::AdvancePrefetch;
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steps.push_back(step);
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step.microcycle.length = HalfCycles(3);
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step.microcycle.operation |= Microcycle::SelectWord | Microcycle::Read | Microcycle::IsProgram;
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step.action = Action::IncrementProgramCounter;
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steps.push_back(step);
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access_pattern += 2;
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break;
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case 'r': // Fetch LSW (or only) word (/byte)
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case 'R': // Fetch MSW word
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case 'w': // Store LSW (or only) word (/byte)
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case 'W': { // Store MSW word
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const bool is_read = tolower(access_pattern[1]) == 'r';
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RegisterPair32 **scratch_data = is_read ? &scratch_data_read : &scratch_data_write;
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step.microcycle.length = HalfCycles(5);
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step.microcycle.operation = Microcycle::NewAddress | (is_read ? Microcycle::Read : 0);
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step.microcycle.address = *address_iterator;
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step.microcycle.value = isupper(access_pattern[1]) ? &(*scratch_data)->halves.high : &(*scratch_data)->halves.low;
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steps.push_back(step);
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step.microcycle.length = HalfCycles(3);
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step.microcycle.operation |= (read_full_words ? Microcycle::SelectWord : Microcycle::SelectByte) | (is_read ? Microcycle::Read : 0);
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if(access_pattern[1] == 'R') {
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step.action = Action::IncrementEffectiveAddress0;
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}
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if(access_pattern[1] == 'W') {
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step.action = Action::IncrementEffectiveAddress1;
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}
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steps.push_back(step);
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if(!isupper(access_pattern[1])) {
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++(*scratch_data);
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++address_iterator;
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}
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access_pattern += 2;
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} break;
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}
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break;
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case '_': // Indicates the reset cycle.
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step.microcycle.length = HalfCycles(248);
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step.microcycle.operation = Microcycle::Reset;
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// Do nothing (possibly twice).
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if(token == "n" || token == "nn") {
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steps.push_back(step);
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if(token.size() == 2) {
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steps.push_back(step);
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++access_pattern;
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break;
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default:
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std::cerr << "MC68000 program builder; Unknown access type " << *access_pattern << std::endl;
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assert(false);
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}
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continue;
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}
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// Fetch SSP.
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if(token == "nF" || token == "nf") {
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step.microcycle.length = HalfCycles(5);
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step.microcycle.operation = Microcycle::NewAddress | Microcycle::Read | Microcycle::IsProgram; // IsProgram is a guess.
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step.microcycle.address = &storage_.effective_address_[0].full;
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step.microcycle.value = isupper(token[1]) ? &storage_.stack_pointers_[1].halves.high : &storage_.stack_pointers_[1].halves.low;
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steps.push_back(step);
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step.microcycle.length = HalfCycles(3);
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step.microcycle.operation = Microcycle::SelectWord | Microcycle::Read | Microcycle::IsProgram;
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step.action = Action::IncrementEffectiveAddress0;
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steps.push_back(step);
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continue;
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}
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// Fetch exception vector.
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if(token == "nV" || token == "nv") {
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step.microcycle.length = HalfCycles(5);
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step.microcycle.operation = Microcycle::NewAddress | Microcycle::Read | Microcycle::IsProgram; // IsProgram is a guess.
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step.microcycle.address = &storage_.effective_address_[0].full;
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step.microcycle.value = isupper(token[1]) ? &storage_.program_counter_.halves.high : &storage_.program_counter_.halves.low;
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steps.push_back(step);
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step.microcycle.length = HalfCycles(3);
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step.microcycle.operation |= Microcycle::SelectWord | Microcycle::Read | Microcycle::IsProgram;
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step.action = Action::IncrementEffectiveAddress0;
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steps.push_back(step);
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continue;
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}
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// Fetch from the program counter into the prefetch queue.
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if(token == "np") {
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step.microcycle.length = HalfCycles(5);
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step.microcycle.operation = Microcycle::NewAddress | Microcycle::Read | Microcycle::IsProgram;
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step.microcycle.address = &storage_.program_counter_.full;
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step.microcycle.value = &storage_.prefetch_queue_.halves.low;
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step.action = Action::AdvancePrefetch;
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steps.push_back(step);
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step.microcycle.length = HalfCycles(3);
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step.microcycle.operation |= Microcycle::SelectWord | Microcycle::Read | Microcycle::IsProgram;
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step.action = Action::IncrementProgramCounter;
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steps.push_back(step);
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continue;
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}
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// The reset cycle.
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if(token == "_") {
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step.microcycle.length = HalfCycles(248);
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step.microcycle.operation = Microcycle::Reset;
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steps.push_back(step);
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continue;
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}
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// A standard read or write.
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if(token == "nR" || token == "nr" || token == "nW" || token == "nw") {
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const bool is_read = tolower(access_pattern[1]) == 'r';
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RegisterPair32 **scratch_data = is_read ? &scratch_data_read : &scratch_data_write;
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step.microcycle.length = HalfCycles(5);
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step.microcycle.operation = Microcycle::NewAddress | (is_read ? Microcycle::Read : 0);
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step.microcycle.address = *address_iterator;
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step.microcycle.value = isupper(token[1]) ? &(*scratch_data)->halves.high : &(*scratch_data)->halves.low;
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steps.push_back(step);
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step.microcycle.length = HalfCycles(3);
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step.microcycle.operation |= (read_full_words ? Microcycle::SelectWord : Microcycle::SelectByte) | (is_read ? Microcycle::Read : 0);
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if(token[1] == 'R') {
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step.action = Action::IncrementEffectiveAddress0;
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}
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if(token[1] == 'W') {
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step.action = Action::IncrementEffectiveAddress1;
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}
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steps.push_back(step);
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if(!isupper(access_pattern[1])) {
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++(*scratch_data);
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++address_iterator;
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}
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continue;
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}
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std::cerr << "MC68000 program builder; Unknown access token " << token << std::endl;
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assert(false);
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}
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// Add a final 'ScheduleNextProgram' sentinel.
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