mirror of
https://github.com/TomHarte/CLK.git
synced 2025-04-09 00:37:27 +00:00
Expand decode to accept a wider array of operations, and then funnel them down.
This commit is contained in:
Thomas Harte
parent
3d5986c55d
commit
cc4431c409
@ -24,7 +24,24 @@ constexpr AddressingMode combined_mode(int mode, int reg) {
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// MARK: - Instruction decoders.
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template <Operation operation> Preinstruction Predecoder::decode(uint16_t instruction) {
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constexpr Operation Predecoder::operation(uint8_t op) {
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if(op < uint8_t(Operation::Max)) {
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return Operation(op);
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}
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switch(op) {
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case MOVEMtoRl: case MOVEMtoMl: return Operation::MOVEMl;
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case MOVEMtoRw: case MOVEMtoMw: return Operation::MOVEMw;
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case MOVEPtoRl: case MOVEPtoMl: return Operation::MOVEPl;
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case MOVEPtoRw: case MOVEPtoMw: return Operation::MOVEPw;
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default: break;
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}
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return Operation::Undefined;
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}
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template <uint8_t op> Preinstruction Predecoder::decode(uint16_t instruction) {
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// Fields used pervasively below.
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//
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// Underlying assumption: the compiler will discard whatever of these
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@ -35,13 +52,14 @@ template <Operation operation> Preinstruction Predecoder::decode(uint16_t instru
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const auto opmode = (instruction >> 6) & 7;
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const auto data_register = (instruction >> 9) & 7;
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constexpr auto operation = Predecoder::operation(op);
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switch(operation) {
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switch(op) {
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//
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// MARK: ABCD, SBCD.
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//
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case Operation::ABCD: case Operation::SBCD: {
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case uint8_t(Operation::ABCD): case uint8_t(Operation::SBCD): {
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const auto addressing_mode = (instruction & 8) ?
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AddressingMode::AddressRegisterIndirectWithPredecrement : AddressingMode::DataRegisterDirect;
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@ -53,15 +71,18 @@ template <Operation operation> Preinstruction Predecoder::decode(uint16_t instru
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//
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// MARK: AND, OR, EOR.
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//
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case Operation::ANDb: case Operation::ANDw: case Operation::ANDl:
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case Operation::ORb: case Operation::ORw: case Operation::ORl:
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case Operation::EORb: case Operation::EORw: case Operation::EORl: {
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case uint8_t(Operation::ANDb): case uint8_t(Operation::ANDw): case uint8_t(Operation::ANDl):
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case uint8_t(Operation::ORb): case uint8_t(Operation::ORw): case uint8_t(Operation::ORl):
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case uint8_t(Operation::EORb): case uint8_t(Operation::EORw): case uint8_t(Operation::EORl): {
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// Opmode 7 is illegal.
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if(opmode == 7) {
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return Preinstruction();
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}
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constexpr bool is_eor = operation == Operation::EORb || operation == Operation::EORw || operation == Operation::EORl;
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constexpr bool is_eor =
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operation == Operation::EORb ||
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operation == Operation::EORw ||
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operation == Operation::EORl;
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if(opmode & 4) {
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// Dn Λ < ea > → < ea >
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@ -97,7 +118,7 @@ template <Operation operation> Preinstruction Predecoder::decode(uint16_t instru
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//
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// MARK: EXG.
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//
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case Operation::EXG:
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case uint8_t(Operation::EXG):
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switch((instruction >> 3)&31) {
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default: return Preinstruction();
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@ -121,8 +142,8 @@ template <Operation operation> Preinstruction Predecoder::decode(uint16_t instru
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//
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// MARK: MULU, MULS, DIVU, DIVS.
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//
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case Operation::DIVU: case Operation::DIVS:
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case Operation::MULU: case Operation::MULS:
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case uint8_t(Operation::DIVU): case uint8_t(Operation::DIVS):
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case uint8_t(Operation::MULU): case uint8_t(Operation::MULS):
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return Preinstruction(operation,
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ea_combined_mode, ea_register,
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AddressingMode::DataRegisterDirect, data_register);
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@ -130,9 +151,9 @@ template <Operation operation> Preinstruction Predecoder::decode(uint16_t instru
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//
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// MARK: ORItoCCR, ORItoSR, ANDItoCCR, ANDItoSR, EORItoCCR, EORItoSR
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//
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case Operation::ORItoSR: case Operation::ORItoCCR:
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case Operation::ANDItoSR: case Operation::ANDItoCCR:
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case Operation::EORItoSR: case Operation::EORItoCCR:
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case uint8_t(Operation::ORItoSR): case uint8_t(Operation::ORItoCCR):
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case uint8_t(Operation::ANDItoSR): case uint8_t(Operation::ANDItoCCR):
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case uint8_t(Operation::EORItoSR): case uint8_t(Operation::EORItoCCR):
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return Preinstruction(operation,
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AddressingMode::ImmediateData, 0,
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operation == Operation::ORItoSR || operation == Operation::ANDItoSR || operation == Operation::EORItoSR);
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@ -140,22 +161,16 @@ template <Operation operation> Preinstruction Predecoder::decode(uint16_t instru
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//
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// MARK: MOVEPtoRw, MOVEPtoRl
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//
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case Operation::MOVEPtoRw: case Operation::MOVEPtoRl:
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case MOVEPtoRw: case MOVEPtoRl:
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return Preinstruction(operation,
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AddressingMode::AddressRegisterIndirectWithDisplacement, ea_register,
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AddressingMode::DataRegisterDirect, data_register);
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case Operation::MOVEPtoMw: case Operation::MOVEPtoMl:
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case MOVEPtoMw: case MOVEPtoMl:
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return Preinstruction(operation,
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AddressingMode::DataRegisterDirect, data_register,
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AddressingMode::AddressRegisterIndirectWithDisplacement, ea_register);
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// TODO: there's no need for separate toR and toM given that source and dest are specified overtly.
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// Between this and the ANDI/etc case, probably this template needs to take a type other than Operation?
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// That'll be a slight hassle because it couldn't inherit from Operation and therefore would either need
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// to duplicate it or in some potentially-fragile way avoid collisions with it. Not to mention all the
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// casting that'd have to be around. So probably duplicate?
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//
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// MARK: Impossible error case.
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//
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@ -172,14 +187,17 @@ template <Operation operation> Preinstruction Predecoder::decode(uint16_t instru
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// MARK: - Page decoders.
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#define DecodeOp(y) return decode<uint8_t(Operation::y)>(instruction)
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#define DecodeEop(y) return decode<y>(instruction)
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Preinstruction Predecoder::decode0(uint16_t instruction) {
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switch(instruction & 0xfff) {
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case 0x03c: return decode<Operation::ORItoCCR>(instruction); // 4-155 (p259)
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case 0x07c: return decode<Operation::ORItoSR>(instruction); // 6-27 (p646)
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case 0x23c: return decode<Operation::ANDItoCCR>(instruction); // 4-20 (p124)
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case 0x27c: return decode<Operation::ANDItoSR>(instruction); // 6-2 (p456)
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case 0xa3c: return decode<Operation::EORItoCCR>(instruction); // 4-104 (p208)
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case 0xa7c: return decode<Operation::EORItoSR>(instruction); // 6-10 (p464)
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case 0x03c: DecodeOp(ORItoCCR); // 4-155 (p259)
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case 0x07c: DecodeOp(ORItoSR); // 6-27 (p646)
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case 0x23c: DecodeOp(ANDItoCCR); // 4-20 (p124)
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case 0x27c: DecodeOp(ANDItoSR); // 6-2 (p456)
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case 0xa3c: DecodeOp(EORItoCCR); // 4-104 (p208)
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case 0xa7c: DecodeOp(EORItoSR); // 6-10 (p464)
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default: break;
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}
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@ -188,66 +206,66 @@ Preinstruction Predecoder::decode0(uint16_t instruction) {
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// versions here, rather than having it determined dynamically in decode.
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switch(instruction & 0xfc0) {
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// 4-153 (p257)
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case 0x000: return decode<Operation::ORb>(instruction);
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case 0x040: return decode<Operation::ORw>(instruction);
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case 0x080: return decode<Operation::ORl>(instruction);
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case 0x000: DecodeOp(ORb);
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case 0x040: DecodeOp(ORw);
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case 0x080: DecodeOp(ORl);
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// 4-18 (p122)
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case 0x200: return decode<Operation::ANDb>(instruction);
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case 0x240: return decode<Operation::ANDw>(instruction);
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case 0x280: return decode<Operation::ANDl>(instruction);
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case 0x200: DecodeOp(ANDb);
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case 0x240: DecodeOp(ANDw);
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case 0x280: DecodeOp(ANDl);
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// 4-179 (p283)
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case 0x400: return decode<Operation::SUBb>(instruction);
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case 0x440: return decode<Operation::SUBw>(instruction);
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case 0x480: return decode<Operation::SUBl>(instruction);
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case 0x400: DecodeOp(SUBb);
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case 0x440: DecodeOp(SUBw);
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case 0x480: DecodeOp(SUBl);
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// 4-9 (p113)
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case 0x600: return decode<Operation::ADDb>(instruction);
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case 0x640: return decode<Operation::ADDw>(instruction);
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case 0x680: return decode<Operation::ADDl>(instruction);
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case 0x600: DecodeOp(ADDb);
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case 0x640: DecodeOp(ADDw);
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case 0x680: DecodeOp(ADDl);
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// 4-63 (p167)
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case 0x800: return decode<Operation::BTSTb>(instruction);
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case 0x800: DecodeOp(BTSTb);
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// 4-29 (p133)
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case 0x840: return decode<Operation::BCHGb>(instruction);
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case 0x840: DecodeOp(BCHGb);
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// 4-32 (p136)
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case 0x880: return decode<Operation::BCLRb>(instruction);
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case 0x880: DecodeOp(BCLRb);
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// 4-58 (p162)
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case 0x8c0: return decode<Operation::BSETb>(instruction);
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case 0x8c0: DecodeOp(BSETb);
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// 4-102 (p206)
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case 0xa00: return decode<Operation::EORb>(instruction);
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case 0xa40: return decode<Operation::EORw>(instruction);
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case 0xa80: return decode<Operation::EORl>(instruction);
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case 0xa00: DecodeOp(EORb);
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case 0xa40: DecodeOp(EORw);
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case 0xa80: DecodeOp(EORl);
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// 4-79 (p183)
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case 0xc00: return decode<Operation::CMPb>(instruction);
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case 0xc40: return decode<Operation::CMPw>(instruction);
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case 0xc80: return decode<Operation::CMPl>(instruction);
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case 0xc00: DecodeOp(CMPb);
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case 0xc40: DecodeOp(CMPw);
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case 0xc80: DecodeOp(CMPl);
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default: break;
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}
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switch(instruction & 0x1c0) {
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case 0x100: return decode<Operation::BTSTb>(instruction); // 4-62 (p166)
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case 0x180: return decode<Operation::BCLRb>(instruction); // 4-31 (p135)
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case 0x100: DecodeOp(BTSTb); // 4-62 (p166)
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case 0x180: DecodeOp(BCLRb); // 4-31 (p135)
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case 0x140: return decode<Operation::BCHGb>(instruction); // 4-28 (p132)
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case 0x1c0: return decode<Operation::BSETb>(instruction); // 4-57 (p161)
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case 0x140: DecodeOp(BCHGb); // 4-28 (p132)
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case 0x1c0: DecodeOp(BSETb); // 4-57 (p161)
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default: break;
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}
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switch(instruction & 0x1f8) {
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// 4-133 (p237)
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case 0x108: return decode<Operation::MOVEPtoRw>(instruction);
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case 0x148: return decode<Operation::MOVEPtoRl>(instruction);
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case 0x188: return decode<Operation::MOVEPtoMw>(instruction);
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case 0x1c8: return decode<Operation::MOVEPtoMl>(instruction);
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case 0x108: DecodeEop(MOVEPtoRw);
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case 0x148: DecodeEop(MOVEPtoRl);
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case 0x188: DecodeEop(MOVEPtoMw);
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case 0x1c8: DecodeEop(MOVEPtoMl);
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default: break;
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}
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@ -256,106 +274,106 @@ Preinstruction Predecoder::decode0(uint16_t instruction) {
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}
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Preinstruction Predecoder::decode1(uint16_t instruction) {
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return decode<Operation::MOVEb>(instruction);
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DecodeOp(MOVEb);
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}
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Preinstruction Predecoder::decode2(uint16_t instruction) {
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return decode<Operation::MOVEl>(instruction);
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DecodeOp(MOVEl);
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}
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Preinstruction Predecoder::decode3(uint16_t instruction) {
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return decode<Operation::MOVEw>(instruction);
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DecodeOp(MOVEw);
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}
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Preinstruction Predecoder::decode4(uint16_t instruction) {
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switch(instruction & 0xfff) {
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case 0xe70: return decode<Operation::RESET>(instruction); // 6-83 (p537)
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case 0xe71: return decode<Operation::NOP>(instruction); // 8-13 (p469)
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case 0xe73: return decode<Operation::RTE>(instruction); // 6-84 (p538)
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case 0xe75: return decode<Operation::RTS>(instruction); // 4-169 (p273)
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case 0xe76: return decode<Operation::TRAPV>(instruction); // 4-191 (p295)
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case 0xe77: return decode<Operation::RTR>(instruction); // 4-168 (p272)
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case 0xe70: DecodeOp(RESET); // 6-83 (p537)
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case 0xe71: DecodeOp(NOP); // 8-13 (p469)
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case 0xe73: DecodeOp(RTE); // 6-84 (p538)
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case 0xe75: DecodeOp(RTS); // 4-169 (p273)
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case 0xe76: DecodeOp(TRAPV); // 4-191 (p295)
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case 0xe77: DecodeOp(RTR); // 4-168 (p272)
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default: break;
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}
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switch(instruction & 0xfc0) {
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// 4-146 (p250)
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case 0x000: return decode<Operation::NEGXb>(instruction);
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case 0x040: return decode<Operation::NEGXw>(instruction);
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case 0x080: return decode<Operation::NEGXl>(instruction);
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case 0x000: DecodeOp(NEGXb);
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case 0x040: DecodeOp(NEGXw);
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case 0x080: DecodeOp(NEGXl);
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// 6-17 (p471)
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case 0x0c0: return decode<Operation::MOVEfromSR>(instruction);
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case 0x0c0: DecodeOp(MOVEfromSR);
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// 4-73 (p177)
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case 0x200: return decode<Operation::CLRb>(instruction);
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case 0x240: return decode<Operation::CLRw>(instruction);
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case 0x280: return decode<Operation::CLRl>(instruction);
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case 0x200: DecodeOp(CLRb);
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case 0x240: DecodeOp(CLRw);
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case 0x280: DecodeOp(CLRl);
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// 4-144 (p248)
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case 0x400: return decode<Operation::NEGb>(instruction);
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case 0x440: return decode<Operation::NEGw>(instruction);
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case 0x480: return decode<Operation::NEGl>(instruction);
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case 0x400: DecodeOp(NEGb);
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case 0x440: DecodeOp(NEGw);
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case 0x480: DecodeOp(NEGl);
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// 4-123 (p227)
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case 0x4c0: return decode<Operation::MOVEtoCCR>(instruction);
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case 0x4c0: DecodeOp(MOVEtoCCR);
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// 4-148 (p250)
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case 0x600: return decode<Operation::NOTb>(instruction);
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case 0x640: return decode<Operation::NOTw>(instruction);
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case 0x680: return decode<Operation::NOTl>(instruction);
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case 0x600: DecodeOp(NOTb);
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case 0x640: DecodeOp(NOTw);
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case 0x680: DecodeOp(NOTl);
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// 4-123 (p227)
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case 0x6c0: return decode<Operation::MOVEtoSR>(instruction);
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case 0x6c0: DecodeOp(MOVEtoSR);
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// 4-142 (p246)
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case 0x800: return decode<Operation::NBCD>(instruction);
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case 0x800: DecodeOp(NBCD);
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// 4-159 (p263)
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case 0x840: return decode<Operation::PEA>(instruction);
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case 0x840: DecodeOp(PEA);
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// 4-128 (p232)
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case 0x880: return decode<Operation::MOVEMtoMw>(instruction);
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case 0x8c0: return decode<Operation::MOVEMtoMl>(instruction);
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case 0xc80: return decode<Operation::MOVEMtoRw>(instruction);
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case 0xcc0: return decode<Operation::MOVEMtoRl>(instruction);
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case 0x880: DecodeEop(MOVEMtoMw);
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case 0x8c0: DecodeEop(MOVEMtoMl);
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case 0xc80: DecodeEop(MOVEMtoRw);
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case 0xcc0: DecodeEop(MOVEMtoRl);
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// 4-192 (p296)
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case 0xa00: return decode<Operation::TSTb>(instruction);
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case 0xa40: return decode<Operation::TSTw>(instruction);
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case 0xa80: return decode<Operation::TSTl>(instruction);
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case 0xa00: DecodeOp(TSTb);
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case 0xa40: DecodeOp(TSTw);
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case 0xa80: DecodeOp(TSTl);
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// 4-186 (p290)
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case 0xac0: return decode<Operation::TAS>(instruction);
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case 0xac0: DecodeOp(TAS);
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// 4-109 (p213)
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case 0xe80: return decode<Operation::JSR>(instruction);
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case 0xe80: DecodeOp(JSR);
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// 4-108 (p212)
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case 0xec0: return decode<Operation::JMP>(instruction);
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case 0xec0: DecodeOp(JMP);
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default: break;
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}
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switch(instruction & 0x1c0) {
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case 0x1c0: return decode<Operation::MOVEAl>(instruction); // 4-110 (p214)
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case 0x180: return decode<Operation::CHK>(instruction); // 4-69 (p173)
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case 0x1c0: DecodeOp(MOVEAl); // 4-110 (p214)
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case 0x180: DecodeOp(CHK); // 4-69 (p173)
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default: break;
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}
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switch(instruction & 0xff0) {
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case 0xe40: return decode<Operation::TRAP>(instruction); // 4-188 (p292)
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case 0xe40: DecodeOp(TRAP); // 4-188 (p292)
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default: break;
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}
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switch(instruction & 0xff8) {
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case 0x860: return decode<Operation::SWAP>(instruction); // 4-185 (p289)
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case 0x880: return decode<Operation::EXTbtow>(instruction); // 4-106 (p210)
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case 0x8c0: return decode<Operation::EXTwtol>(instruction); // 4-106 (p210)
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case 0xe50: return decode<Operation::LINK>(instruction); // 4-111 (p215)
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case 0xe58: return decode<Operation::UNLINK>(instruction); // 4-194 (p298)
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case 0xe60: return decode<Operation::MOVEtoUSP>(instruction); // 6-21 (p475)
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case 0xe68: return decode<Operation::MOVEfromUSP>(instruction); // 6-21 (p475)
|
||||
case 0x860: DecodeOp(SWAP); // 4-185 (p289)
|
||||
case 0x880: DecodeOp(EXTbtow); // 4-106 (p210)
|
||||
case 0x8c0: DecodeOp(EXTwtol); // 4-106 (p210)
|
||||
case 0xe50: DecodeOp(LINK); // 4-111 (p215)
|
||||
case 0xe58: DecodeOp(UNLINK); // 4-194 (p298)
|
||||
case 0xe60: DecodeOp(MOVEtoUSP); // 6-21 (p475)
|
||||
case 0xe68: DecodeOp(MOVEfromUSP); // 6-21 (p475)
|
||||
default: break;
|
||||
}
|
||||
|
||||
@ -365,21 +383,21 @@ Preinstruction Predecoder::decode4(uint16_t instruction) {
|
||||
Preinstruction Predecoder::decode5(uint16_t instruction) {
|
||||
switch(instruction & 0x1c0) {
|
||||
// 4-11 (p115)
|
||||
case 0x000: return decode<Operation::ADDQb>(instruction);
|
||||
case 0x040: return decode<Operation::ADDQw>(instruction);
|
||||
case 0x080: return decode<Operation::ADDQl>(instruction);
|
||||
case 0x000: DecodeOp(ADDQb);
|
||||
case 0x040: DecodeOp(ADDQw);
|
||||
case 0x080: DecodeOp(ADDQl);
|
||||
|
||||
// 4-181 (p285)
|
||||
case 0x100: return decode<Operation::SUBQb>(instruction);
|
||||
case 0x140: return decode<Operation::SUBQw>(instruction);
|
||||
case 0x180: return decode<Operation::SUBQl>(instruction);
|
||||
case 0x100: DecodeOp(SUBQb);
|
||||
case 0x140: DecodeOp(SUBQw);
|
||||
case 0x180: DecodeOp(SUBQl);
|
||||
|
||||
default: break;
|
||||
}
|
||||
|
||||
switch(instruction & 0x0c0) {
|
||||
// 4-173 (p276), though this'll also hit DBcc 4-91 (p195)
|
||||
case 0x0c0: return decode<Operation::Scc>(instruction);
|
||||
case 0x0c0: DecodeOp(Scc);
|
||||
|
||||
default: break;
|
||||
}
|
||||
@ -388,29 +406,29 @@ Preinstruction Predecoder::decode5(uint16_t instruction) {
|
||||
|
||||
Preinstruction Predecoder::decode6(uint16_t instruction) {
|
||||
// 4-25 (p129), 4-59 (p163) and 4-55 (p159)
|
||||
return decode<Operation::Bcc>(instruction);
|
||||
DecodeOp(Bcc);
|
||||
}
|
||||
|
||||
Preinstruction Predecoder::decode7(uint16_t instruction) {
|
||||
// 4-134 (p238)
|
||||
return decode<Operation::MOVEq>(instruction);
|
||||
DecodeOp(MOVEq);
|
||||
}
|
||||
|
||||
Preinstruction Predecoder::decode8(uint16_t instruction) {
|
||||
// 4-171 (p275)
|
||||
if((instruction & 0x1f0) == 0x100) return decode<Operation::SBCD>(instruction);
|
||||
if((instruction & 0x1f0) == 0x100) DecodeOp(SBCD);
|
||||
|
||||
// 4-150 (p254)
|
||||
switch(instruction & 0x0c0) {
|
||||
case 0x00: return decode<Operation::ORb>(instruction);
|
||||
case 0x40: return decode<Operation::ORw>(instruction);
|
||||
case 0x80: return decode<Operation::ORl>(instruction);
|
||||
case 0x00: DecodeOp(ORb);
|
||||
case 0x40: DecodeOp(ORw);
|
||||
case 0x80: DecodeOp(ORl);
|
||||
default: break;
|
||||
}
|
||||
|
||||
switch(instruction & 0x1c0) {
|
||||
case 0x0c0: return decode<Operation::DIVU>(instruction); // 4-97 (p201)
|
||||
case 0x1c0: return decode<Operation::DIVS>(instruction); // 4-93 (p197)
|
||||
case 0x0c0: DecodeOp(DIVU); // 4-97 (p201)
|
||||
case 0x1c0: DecodeOp(DIVS); // 4-93 (p197)
|
||||
default: break;
|
||||
}
|
||||
|
||||
@ -420,26 +438,26 @@ Preinstruction Predecoder::decode8(uint16_t instruction) {
|
||||
Preinstruction Predecoder::decode9(uint16_t instruction) {
|
||||
switch(instruction & 0x0c0) {
|
||||
// 4-174 (p278)
|
||||
case 0x00: return decode<Operation::SUBb>(instruction);
|
||||
case 0x40: return decode<Operation::SUBw>(instruction);
|
||||
case 0x80: return decode<Operation::SUBl>(instruction);
|
||||
case 0x00: DecodeOp(SUBb);
|
||||
case 0x40: DecodeOp(SUBw);
|
||||
case 0x80: DecodeOp(SUBl);
|
||||
|
||||
default: break;
|
||||
}
|
||||
|
||||
switch(instruction & 0x1c0) {
|
||||
// 4-177 (p281)
|
||||
case 0x0c0: return decode<Operation::SUBAw>(instruction);
|
||||
case 0x1c0: return decode<Operation::SUBAl>(instruction);
|
||||
case 0x0c0: DecodeOp(SUBAw);
|
||||
case 0x1c0: DecodeOp(SUBAl);
|
||||
|
||||
default: break;
|
||||
}
|
||||
|
||||
switch(instruction & 0x1f0) {
|
||||
// 4-184 (p288)
|
||||
case 0x100: return decode<Operation::SUBXb>(instruction);
|
||||
case 0x140: return decode<Operation::SUBXw>(instruction);
|
||||
case 0x180: return decode<Operation::SUBXl>(instruction);
|
||||
case 0x100: DecodeOp(SUBXb);
|
||||
case 0x140: DecodeOp(SUBXw);
|
||||
case 0x180: DecodeOp(SUBXl);
|
||||
|
||||
default: break;
|
||||
}
|
||||
@ -454,21 +472,21 @@ Preinstruction Predecoder::decodeA(uint16_t) {
|
||||
Preinstruction Predecoder::decodeB(uint16_t instruction) {
|
||||
switch(instruction & 0x0c0) {
|
||||
// 4-100 (p204)
|
||||
case 0x000: return decode<Operation::EORb>(instruction);
|
||||
case 0x040: return decode<Operation::EORw>(instruction);
|
||||
case 0x080: return decode<Operation::EORl>(instruction);
|
||||
case 0x000: DecodeOp(EORb);
|
||||
case 0x040: DecodeOp(EORw);
|
||||
case 0x080: DecodeOp(EORl);
|
||||
default: break;
|
||||
}
|
||||
|
||||
switch(instruction & 0x1c0) {
|
||||
// 4-75 (p179)
|
||||
case 0x000: return decode<Operation::CMPb>(instruction);
|
||||
case 0x040: return decode<Operation::CMPw>(instruction);
|
||||
case 0x080: return decode<Operation::CMPl>(instruction);
|
||||
case 0x000: DecodeOp(CMPb);
|
||||
case 0x040: DecodeOp(CMPw);
|
||||
case 0x080: DecodeOp(CMPl);
|
||||
|
||||
// 4-77 (p181)
|
||||
case 0x0c0: return decode<Operation::CMPAw>(instruction);
|
||||
case 0x1c0: return decode<Operation::CMPAl>(instruction);
|
||||
case 0x0c0: DecodeOp(CMPAw);
|
||||
case 0x1c0: DecodeOp(CMPAl);
|
||||
|
||||
default: break;
|
||||
}
|
||||
@ -478,21 +496,21 @@ Preinstruction Predecoder::decodeB(uint16_t instruction) {
|
||||
|
||||
Preinstruction Predecoder::decodeC(uint16_t instruction) {
|
||||
switch(instruction & 0x1f0) {
|
||||
case 0x100: return decode<Operation::ABCD>(instruction); // 4-3 (p107)
|
||||
case 0x100: DecodeOp(ABCD); // 4-3 (p107)
|
||||
default: break;
|
||||
}
|
||||
|
||||
switch(instruction & 0x0c0) {
|
||||
// 4-15 (p119)
|
||||
case 0x00: return decode<Operation::ANDb>(instruction);
|
||||
case 0x40: return decode<Operation::ANDw>(instruction);
|
||||
case 0x80: return decode<Operation::ANDl>(instruction);
|
||||
case 0x00: DecodeOp(ANDb);
|
||||
case 0x40: DecodeOp(ANDw);
|
||||
case 0x80: DecodeOp(ANDl);
|
||||
default: break;
|
||||
}
|
||||
|
||||
switch(instruction & 0x1c0) {
|
||||
case 0x0c0: return decode<Operation::MULU>(instruction); // 4-139 (p243)
|
||||
case 0x1c0: return decode<Operation::MULS>(instruction); // 4-136 (p240)
|
||||
case 0x0c0: DecodeOp(MULU); // 4-139 (p243)
|
||||
case 0x1c0: DecodeOp(MULS); // 4-136 (p240)
|
||||
default: break;
|
||||
}
|
||||
|
||||
@ -500,7 +518,7 @@ Preinstruction Predecoder::decodeC(uint16_t instruction) {
|
||||
switch(instruction & 0x1f8) {
|
||||
case 0x140:
|
||||
case 0x148:
|
||||
case 0x188: return decode<Operation::EXG>(instruction);
|
||||
case 0x188: DecodeOp(EXG);
|
||||
default: break;
|
||||
}
|
||||
|
||||
@ -510,26 +528,26 @@ Preinstruction Predecoder::decodeC(uint16_t instruction) {
|
||||
Preinstruction Predecoder::decodeD(uint16_t instruction) {
|
||||
switch(instruction & 0x0c0) {
|
||||
// 4-4 (p108)
|
||||
case 0x000: return decode<Operation::ADDb>(instruction);
|
||||
case 0x040: return decode<Operation::ADDw>(instruction);
|
||||
case 0x080: return decode<Operation::ADDl>(instruction);
|
||||
case 0x000: DecodeOp(ADDb);
|
||||
case 0x040: DecodeOp(ADDw);
|
||||
case 0x080: DecodeOp(ADDl);
|
||||
|
||||
default: break;
|
||||
}
|
||||
|
||||
switch(instruction & 0x1c0) {
|
||||
// 4-7 (p111)
|
||||
case 0x0c0: return decode<Operation::ADDAw>(instruction);
|
||||
case 0x1c0: return decode<Operation::ADDAl>(instruction);
|
||||
case 0x0c0: DecodeOp(ADDAw);
|
||||
case 0x1c0: DecodeOp(ADDAl);
|
||||
|
||||
default: break;
|
||||
}
|
||||
|
||||
switch(instruction & 0x1f0) {
|
||||
// 4-14 (p118)
|
||||
case 0x100: return decode<Operation::ADDXb>(instruction);
|
||||
case 0x140: return decode<Operation::ADDXw>(instruction);
|
||||
case 0x180: return decode<Operation::ADDXl>(instruction);
|
||||
case 0x100: DecodeOp(ADDXb);
|
||||
case 0x140: DecodeOp(ADDXw);
|
||||
case 0x180: DecodeOp(ADDXl);
|
||||
|
||||
default: break;
|
||||
}
|
||||
@ -540,57 +558,57 @@ Preinstruction Predecoder::decodeD(uint16_t instruction) {
|
||||
Preinstruction Predecoder::decodeE(uint16_t instruction) {
|
||||
switch(instruction & 0x1d8) {
|
||||
// 4-22 (p126)
|
||||
case 0x000: return decode<Operation::ASRb>(instruction);
|
||||
case 0x040: return decode<Operation::ASRw>(instruction);
|
||||
case 0x080: return decode<Operation::ASRl>(instruction);
|
||||
case 0x000: DecodeOp(ASRb);
|
||||
case 0x040: DecodeOp(ASRw);
|
||||
case 0x080: DecodeOp(ASRl);
|
||||
|
||||
// 4-113 (p217)
|
||||
case 0x008: return decode<Operation::LSRb>(instruction);
|
||||
case 0x048: return decode<Operation::LSRw>(instruction);
|
||||
case 0x088: return decode<Operation::LSRl>(instruction);
|
||||
case 0x008: DecodeOp(LSRb);
|
||||
case 0x048: DecodeOp(LSRw);
|
||||
case 0x088: DecodeOp(LSRl);
|
||||
|
||||
// 4-163 (p267)
|
||||
case 0x010: return decode<Operation::ROXRb>(instruction);
|
||||
case 0x050: return decode<Operation::ROXRw>(instruction);
|
||||
case 0x090: return decode<Operation::ROXRl>(instruction);
|
||||
case 0x010: DecodeOp(ROXRb);
|
||||
case 0x050: DecodeOp(ROXRw);
|
||||
case 0x090: DecodeOp(ROXRl);
|
||||
|
||||
// 4-160 (p264)
|
||||
case 0x018: return decode<Operation::RORb>(instruction);
|
||||
case 0x058: return decode<Operation::RORw>(instruction);
|
||||
case 0x098: return decode<Operation::RORl>(instruction);
|
||||
case 0x018: DecodeOp(RORb);
|
||||
case 0x058: DecodeOp(RORw);
|
||||
case 0x098: DecodeOp(RORl);
|
||||
|
||||
// 4-22 (p126)
|
||||
case 0x100: return decode<Operation::ASLb>(instruction);
|
||||
case 0x140: return decode<Operation::ASLw>(instruction);
|
||||
case 0x180: return decode<Operation::ASLl>(instruction);
|
||||
case 0x100: DecodeOp(ASLb);
|
||||
case 0x140: DecodeOp(ASLw);
|
||||
case 0x180: DecodeOp(ASLl);
|
||||
|
||||
// 4-113 (p217)
|
||||
case 0x108: return decode<Operation::LSLb>(instruction);
|
||||
case 0x148: return decode<Operation::LSLw>(instruction);
|
||||
case 0x188: return decode<Operation::LSLl>(instruction);
|
||||
case 0x108: DecodeOp(LSLb);
|
||||
case 0x148: DecodeOp(LSLw);
|
||||
case 0x188: DecodeOp(LSLl);
|
||||
|
||||
// 4-163 (p267)
|
||||
case 0x110: return decode<Operation::ROXLb>(instruction);
|
||||
case 0x150: return decode<Operation::ROXLw>(instruction);
|
||||
case 0x190: return decode<Operation::ROXLl>(instruction);
|
||||
case 0x110: DecodeOp(ROXLb);
|
||||
case 0x150: DecodeOp(ROXLw);
|
||||
case 0x190: DecodeOp(ROXLl);
|
||||
|
||||
// 4-160 (p264)
|
||||
case 0x118: return decode<Operation::ROLb>(instruction);
|
||||
case 0x158: return decode<Operation::ROLw>(instruction);
|
||||
case 0x198: return decode<Operation::ROLl>(instruction);
|
||||
case 0x118: DecodeOp(ROLb);
|
||||
case 0x158: DecodeOp(ROLw);
|
||||
case 0x198: DecodeOp(ROLl);
|
||||
|
||||
default: break;
|
||||
}
|
||||
|
||||
switch(instruction & 0xfc0) {
|
||||
case 0x0c0: return decode<Operation::ASRm>(instruction); // 4-22 (p126)
|
||||
case 0x1c0: return decode<Operation::ASLm>(instruction); // 4-22 (p126)
|
||||
case 0x2c0: return decode<Operation::LSRm>(instruction); // 4-113 (p217)
|
||||
case 0x3c0: return decode<Operation::LSLm>(instruction); // 4-113 (p217)
|
||||
case 0x4c0: return decode<Operation::ROXRm>(instruction); // 4-163 (p267)
|
||||
case 0x5c0: return decode<Operation::ROXLm>(instruction); // 4-163 (p267)
|
||||
case 0x6c0: return decode<Operation::RORm>(instruction); // 4-160 (p264)
|
||||
case 0x7c0: return decode<Operation::ROLm>(instruction); // 4-160 (p264)
|
||||
case 0x0c0: DecodeOp(ASRm); // 4-22 (p126)
|
||||
case 0x1c0: DecodeOp(ASLm); // 4-22 (p126)
|
||||
case 0x2c0: DecodeOp(LSRm); // 4-113 (p217)
|
||||
case 0x3c0: DecodeOp(LSLm); // 4-113 (p217)
|
||||
case 0x4c0: DecodeOp(ROXRm); // 4-163 (p267)
|
||||
case 0x5c0: DecodeOp(ROXLm); // 4-163 (p267)
|
||||
case 0x6c0: DecodeOp(RORm); // 4-160 (p264)
|
||||
case 0x7c0: DecodeOp(ROLm); // 4-160 (p264)
|
||||
|
||||
default: break;
|
||||
}
|
||||
@ -602,6 +620,8 @@ Preinstruction Predecoder::decodeF(uint16_t) {
|
||||
return Preinstruction();
|
||||
}
|
||||
|
||||
#undef DecodeOp
|
||||
|
||||
// MARK: - Main decoder.
|
||||
|
||||
Preinstruction Predecoder::decode(uint16_t instruction) {
|
||||
|
||||
@ -44,7 +44,17 @@ class Predecoder {
|
||||
Preinstruction decodeF(uint16_t instruction);
|
||||
|
||||
// Specific instruction decoders.
|
||||
template <Operation operation> Preinstruction decode(uint16_t instruction);
|
||||
template <uint8_t operation> Preinstruction decode(uint16_t instruction);
|
||||
|
||||
enum ExtendedOperation {
|
||||
MOVEMtoRl = uint8_t(Operation::Max), MOVEMtoRw,
|
||||
MOVEMtoMl, MOVEMtoMw,
|
||||
|
||||
MOVEPtoRl, MOVEPtoRw,
|
||||
MOVEPtoMl, MOVEPtoMw,
|
||||
|
||||
};
|
||||
static constexpr Operation operation(uint8_t op);
|
||||
};
|
||||
|
||||
}
|
||||
|
||||
@ -69,11 +69,8 @@ enum class Operation: uint8_t {
|
||||
ROXLb, ROXLw, ROXLl, ROXLm,
|
||||
ROXRb, ROXRw, ROXRl, ROXRm,
|
||||
|
||||
MOVEMtoRl, MOVEMtoRw,
|
||||
MOVEMtoMl, MOVEMtoMw,
|
||||
|
||||
MOVEPtoRl, MOVEPtoRw,
|
||||
MOVEPtoMl, MOVEPtoMw,
|
||||
MOVEMl, MOVEMw,
|
||||
MOVEPl, MOVEPw,
|
||||
|
||||
ANDb, ANDw, ANDl,
|
||||
EORb, EORw, EORl,
|
||||
@ -100,6 +97,8 @@ enum class Operation: uint8_t {
|
||||
LINK, UNLINK,
|
||||
|
||||
STOP, RESET,
|
||||
|
||||
Max = RESET
|
||||
};
|
||||
|
||||
/// Indicates the addressing mode applicable to an operand.
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user