From d01fa96177fcd73f6b5be0168b3ee43e9f1617d5 Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Sun, 24 Apr 2022 20:49:41 -0400
Subject: [PATCH] Port BSR, BTST.

---
 InstructionSets/68k/Decoder.cpp | 40 +++++++++++++++------------------
 1 file changed, 18 insertions(+), 22 deletions(-)

diff --git a/InstructionSets/68k/Decoder.cpp b/InstructionSets/68k/Decoder.cpp
index c539b275d..14b6859b7 100644
--- a/InstructionSets/68k/Decoder.cpp
+++ b/InstructionSets/68k/Decoder.cpp
@@ -228,8 +228,9 @@ template <uint8_t op> uint32_t Predecoder<model>::invalid_operands() {
 				AlterableAddressingModes
 			>::value;
 
-		case OpT(Operation::Bccw):	case OpT(Operation::Bccl):
 		case OpT(Operation::ANDItoCCR):
+		case OpT(Operation::Bccw):	case OpT(Operation::Bccl):
+		case OpT(Operation::BSRl):	case OpT(Operation::BSRw):
 			return ~OneOperandMask<
 				Imm
 			>::value;
@@ -242,6 +243,7 @@ template <uint8_t op> uint32_t Predecoder<model>::invalid_operands() {
 			>::value;
 
 		case OpT(Operation::Bccb):
+		case OpT(Operation::BSRb):
 			return ~OneOperandMask<
 				Quick
 			>::value;
@@ -260,6 +262,18 @@ template <uint8_t op> uint32_t Predecoder<model>::invalid_operands() {
 				AlterableAddressingModesNoAn
 			>::value;
 
+		case OpT(Operation::BTST):
+			return ~TwoOperandMask<
+				Dn,
+				AllModesNoAn
+			>::value;
+
+		case BTSTI:
+			return ~TwoOperandMask<
+				Imm,
+				Dn | Ind | PostInc | PreDec | d16An | d8AnXn | XXXw | XXXl | d16PC | d8PCXn
+			>::value;
+
 		case OpT(Operation::NBCD):
 			return ~OneOperandMask<
 				AlterableAddressingModesNoAn
@@ -297,6 +311,8 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::validated
 		case OpT(Operation::BCHG):	case BCHGI:
 		case OpT(Operation::BCLR):	case BCLRI:
 		case OpT(Operation::BSET):	case BSETI:
+		case OpT(Operation::BSRb):	case OpT(Operation::BSRw):	case OpT(Operation::BSRl):
+		case OpT(Operation::BTST):	case BTSTI:
 		case OpT(Operation::NBCD): {
 			const auto invalid = invalid_operands<op>();
 			const auto observed = operand_mask(original);
@@ -395,8 +411,7 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::validated
 			}
 		}
 
-		case SUBtoRb:		case SUBtoRw:	case SUBtoRl:
-		/*case ADDtoRb:		case ADDtoRw:	case ADDtoRl: */{
+		case SUBtoRb:		case SUBtoRw:	case SUBtoRl: {
 			constexpr bool is_byte = op == ADDtoRb || op == SUBtoRb || op == SUBtoRb || op == ADDtoRb;
 
 			switch(original.mode<0>()) {
@@ -511,25 +526,6 @@ template <uint8_t op, bool validate> Preinstruction Predecoder<model>::validated
 					return Preinstruction();
 			}
 
-		case OpT(Operation::BTST):
-			switch(original.mode<1>()) {
-				default: return original;
-
-				case AddressingMode::None:
-				case AddressingMode::AddressRegisterDirect:
-					return Preinstruction();
-			}
-
-		case BTSTI:
-			switch(original.mode<1>()) {
-				default: return original;
-
-				case AddressingMode::None:
-				case AddressingMode::AddressRegisterDirect:
-				case AddressingMode::ImmediateData:
-					return Preinstruction();
-			}
-
 		case OpT(Operation::TSTb):	case OpT(Operation::TSTw):	case OpT(Operation::TSTl):
 			switch(original.mode<0>()) {
 				default: return original;