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mirror of https://github.com/TomHarte/CLK.git synced 2024-12-23 20:29:42 +00:00

Added test of perfect DPLL input timing.

This commit is contained in:
Thomas Harte 2016-07-12 21:42:23 -04:00
parent 94db45456e
commit d1fe07f14d
7 changed files with 125 additions and 5 deletions

View File

@ -333,6 +333,8 @@
4BC9DF4F1D04691600F44158 /* 6560.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4BC9DF4D1D04691600F44158 /* 6560.cpp */; };
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4BEF6AAC1D35D1C400E73575 /* DPLLTests.swift in Sources */ = {isa = PBXBuildFile; fileRef = 4BEF6AAB1D35D1C400E73575 /* DPLLTests.swift */; };
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@ -737,6 +739,9 @@
4BCA98C21D065CA20062F44C /* 6522.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; path = 6522.hpp; sourceTree = "<group>"; };
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@ -887,13 +892,15 @@
isa = PBXGroup;
children = (
4B3BA0C51D318B44005DD7A7 /* C1540Bridge.h */,
4B3BA0C61D318B44005DD7A7 /* C1540Bridge.mm */,
4B3BA0C71D318B44005DD7A7 /* Clock SignalTests-Bridging-Header.h */,
4BEF6AA81D35CE9E00E73575 /* DigitalPhaseLockedLoopBridge.h */,
4B3BA0C81D318B44005DD7A7 /* MOS6522Bridge.h */,
4B3BA0C91D318B44005DD7A7 /* MOS6522Bridge.mm */,
4B3BA0CA1D318B44005DD7A7 /* MOS6532Bridge.h */,
4B3BA0CB1D318B44005DD7A7 /* MOS6532Bridge.mm */,
4B3BA0CC1D318B44005DD7A7 /* TestMachine.h */,
4B3BA0C61D318B44005DD7A7 /* C1540Bridge.mm */,
4BEF6AA91D35CE9E00E73575 /* DigitalPhaseLockedLoopBridge.mm */,
4B3BA0C91D318B44005DD7A7 /* MOS6522Bridge.mm */,
4B3BA0CB1D318B44005DD7A7 /* MOS6532Bridge.mm */,
4B3BA0CD1D318B44005DD7A7 /* TestMachine.mm */,
);
path = Bridges;
@ -1335,6 +1342,7 @@
4B1E85801D176468001EF87D /* 6532Tests.swift */,
4BB73EB61B587A5100552FC2 /* AllSuiteATests.swift */,
4B3BA0C21D318AEB005DD7A7 /* C1540Tests.swift */,
4BEF6AAB1D35D1C400E73575 /* DPLLTests.swift */,
4B1414611B58888700E04248 /* KlausDormannTests.swift */,
4B14145F1B58885000E04248 /* WolfgangLorenzTests.swift */,
4B3BA0C41D318B44005DD7A7 /* Bridges */,
@ -1903,10 +1911,12 @@
4B14145D1B5887A600E04248 /* CPU6502.cpp in Sources */,
4B1E85811D176468001EF87D /* 6532Tests.swift in Sources */,
4BC9E1EE1D23449A003FCEE4 /* 6502InterruptTests.swift in Sources */,
4BEF6AAA1D35CE9E00E73575 /* DigitalPhaseLockedLoopBridge.mm in Sources */,
4B3BA0CE1D318B44005DD7A7 /* C1540Bridge.mm in Sources */,
4B3BA0D11D318B44005DD7A7 /* TestMachine.mm in Sources */,
4B92EACA1B7C112B00246143 /* 6502TimingTests.swift in Sources */,
4BB73EB71B587A5100552FC2 /* AllSuiteATests.swift in Sources */,
4BEF6AAC1D35D1C400E73575 /* DPLLTests.swift in Sources */,
4B3BA0CF1D318B44005DD7A7 /* MOS6522Bridge.mm in Sources */,
4BC751B21D157E61006C31D9 /* 6522Tests.swift in Sources */,
4B3BA0D01D318B44005DD7A7 /* MOS6532Bridge.mm in Sources */,

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@ -6,3 +6,4 @@
#import "MOS6522Bridge.h"
#import "MOS6532Bridge.h"
#import "C1540Bridge.h"
#import "DigitalPhaseLockedLoopBridge.h"

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@ -0,0 +1,20 @@
//
// DigitalPhaseLockedLoopBridge.h
// Clock Signal
//
// Created by Thomas Harte on 12/07/2016.
// Copyright © 2016 Thomas Harte. All rights reserved.
//
#import <Foundation/Foundation.h>
@interface DigitalPhaseLockedLoopBridge : NSObject
- (instancetype)initWithClocksPerBit:(NSUInteger)clocksPerBit tolerance:(NSUInteger)tolerance historyLength:(NSUInteger)historyLength;
- (void)runForCycles:(NSUInteger)cycles;
- (void)addPulse;
@property(nonatomic) NSUInteger stream;
@end

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@ -0,0 +1,61 @@
//
// DigitalPhaseLockedLoopBridge.m
// Clock Signal
//
// Created by Thomas Harte on 12/07/2016.
// Copyright © 2016 Thomas Harte. All rights reserved.
//
#import "DigitalPhaseLockedLoopBridge.h"
#include "DigitalPhaseLockedLoop.hpp"
#include <memory>
@interface DigitalPhaseLockedLoopBridge(BitPushing)
- (void)pushBit:(int)value;
@end
class DigitalPhaseLockedLoopDelegate: public Storage::DigitalPhaseLockedLoop::Delegate {
public:
__weak DigitalPhaseLockedLoopBridge *bridge;
void digital_phase_locked_loop_output_bit(int value)
{
[bridge pushBit:value ? 1 : 0];
}
};
@implementation DigitalPhaseLockedLoopBridge
{
std::unique_ptr<Storage::DigitalPhaseLockedLoop> _digitalPhaseLockedLoop;
DigitalPhaseLockedLoopDelegate _delegate;
}
- (instancetype)initWithClocksPerBit:(NSUInteger)clocksPerBit tolerance:(NSUInteger)tolerance historyLength:(NSUInteger)historyLength
{
self = [super init];
if(self)
{
_digitalPhaseLockedLoop.reset(new Storage::DigitalPhaseLockedLoop((unsigned int)clocksPerBit, (unsigned int)tolerance, (unsigned int)historyLength));
_delegate.bridge = self;
_digitalPhaseLockedLoop->set_delegate(&_delegate);
}
return self;
}
- (void)runForCycles:(NSUInteger)cycles
{
_digitalPhaseLockedLoop->run_for_cycles((unsigned int)cycles);
}
- (void)addPulse
{
_digitalPhaseLockedLoop->add_pulse();
}
- (void)pushBit:(int)value
{
_stream = (_stream << 1) | value;
}
@end

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@ -0,0 +1,28 @@
//
// DPLLTests.swift
// Clock Signal
//
// Created by Thomas Harte on 12/07/2016.
// Copyright © 2016 Thomas Harte. All rights reserved.
//
import XCTest
class DPLLTests: XCTestCase {
func testPerfectInput() {
let pll = DigitalPhaseLockedLoopBridge(clocksPerBit: 100, tolerance: 20, historyLength: 5)
// clock in two 1s, a 0, and a 1
pll.runForCycles(50)
pll.addPulse()
pll.runForCycles(100)
pll.addPulse()
pll.runForCycles(200)
pll.addPulse()
pll.runForCycles(50)
XCTAssert(pll.stream == 0xd, "PLL should have clocked four bits")
}
}

View File

@ -38,7 +38,7 @@ void DigitalPhaseLockedLoop::run_for_cycles(unsigned int number_of_cycles)
_window_offset %= _current_window_length;
}
// updte timing
// update timing
_next_pulse_time += number_of_cycles;
}

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@ -41,7 +41,7 @@ class DigitalPhaseLockedLoop {
*/
class Delegate {
public:
virtual void digital_phase_locked_loop_output_bit(bool value) = 0;
virtual void digital_phase_locked_loop_output_bit(int value) = 0;
};
void set_delegate(Delegate *delegate)
{