diff --git a/OSBindings/Mac/Clock SignalTests/FUSETests.swift b/OSBindings/Mac/Clock SignalTests/FUSETests.swift index 1aaaf08ff..ac0dcb9fd 100644 --- a/OSBindings/Mac/Clock SignalTests/FUSETests.swift +++ b/OSBindings/Mac/Clock SignalTests/FUSETests.swift @@ -167,7 +167,7 @@ class FUSETests: XCTestCase { let name = itemDictionary["name"] as! String -// if name != "dd36" { +// if name != "66" { // continue; // } @@ -253,7 +253,7 @@ class FUSETests: XCTestCase { capturedBusActivity[capturedBusAcivityIndex].value == value! && capturedBusActivity[capturedBusAcivityIndex].timeStamp == time && capturedBusActivity[capturedBusAcivityIndex].operation == operation, - "Failed bus operation match \(name)") + "Failed bus operation match \(name) (at time \(time) with address \(address), value was \(value != nil ? value! : 0), tracking index \(capturedBusAcivityIndex) amgonst \(capturedBusActivity))") capturedBusAcivityIndex += 1 } } diff --git a/Processors/Z80/Z80AllRAM.cpp b/Processors/Z80/Z80AllRAM.cpp index 84652b392..aafb314d7 100644 --- a/Processors/Z80/Z80AllRAM.cpp +++ b/Processors/Z80/Z80AllRAM.cpp @@ -14,17 +14,18 @@ using namespace CPU::Z80; AllRAMProcessor::AllRAMProcessor() : ::CPU::AllRAMProcessor(65536), delegate_(nullptr) {} int AllRAMProcessor::perform_machine_cycle(const MachineCycle *cycle) { + uint16_t address = cycle->address ? *cycle->address : 0x0000; switch(cycle->operation) { case BusOperation::ReadOpcode: // printf("%04x %02x [BC=%02x]\n", *cycle->address, memory_[*cycle->address], get_value_of_register(CPU::Z80::Register::BC)); - check_address_for_trap(*cycle->address); + check_address_for_trap(address); case BusOperation::Read: // printf("r %04x [%02x] AF:%04x BC:%04x DE:%04x HL:%04x SP:%04x\n", *cycle->address, memory_[*cycle->address], get_value_of_register(CPU::Z80::Register::AF), get_value_of_register(CPU::Z80::Register::BC), get_value_of_register(CPU::Z80::Register::DE), get_value_of_register(CPU::Z80::Register::HL), get_value_of_register(CPU::Z80::Register::StackPointer)); - *cycle->value = memory_[*cycle->address]; + *cycle->value = memory_[address]; break; case BusOperation::Write: // printf("w %04x\n", *cycle->address); - memory_[*cycle->address] = *cycle->value; + memory_[address] = *cycle->value; break; case BusOperation::Output: @@ -32,7 +33,7 @@ int AllRAMProcessor::perform_machine_cycle(const MachineCycle *cycle) { case BusOperation::Input: // This logic is selected specifically because it seems to match // the FUSE unit tests. It might need factoring out. - *cycle->value = (*cycle->address) >> 8; + *cycle->value = address >> 8; break; case BusOperation::Internal: @@ -45,7 +46,7 @@ int AllRAMProcessor::perform_machine_cycle(const MachineCycle *cycle) { timestamp_ += cycle->length; if(delegate_ != nullptr) { - delegate_->z80_all_ram_processor_did_perform_bus_operation(*this, cycle->operation, cycle->address ? *cycle->address : 0x0000, cycle->value ? *cycle->value : 0x00, timestamp_); + delegate_->z80_all_ram_processor_did_perform_bus_operation(*this, cycle->operation, address, cycle->value ? *cycle->value : 0x00, timestamp_); } return 0;