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Proactively attempts to fix CMPM PostInc addressing.
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@ -2289,24 +2289,21 @@ struct ProcessorStorageConstructor {
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case Operation::CMPb: // CMPM.b, (An)+, (An)+
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case Operation::CMPb: // CMPM.b, (An)+, (An)+
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case Operation::CMPw: { // CMPM.w, (An)+, (An)+
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case Operation::CMPw: { // CMPM.w, (An)+, (An)+
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op(Action::None, seq("nr nrd np", { a(data_register), a(ea_register) }, !is_byte_operation));
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op(Action::None, seq("nr", { a(data_register) }, !is_byte_operation));
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op( inc(data_register) | MicroOp::SourceMask,
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seq("nrd np", { a(ea_register) }, !is_byte_operation));
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op(inc(ea_register) | MicroOp::DestinationMask);
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op(Action::PerformOperation);
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op(Action::PerformOperation);
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const int source_inc = inc(ea_register);
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const int destination_inc = inc(data_register);
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if(destination_inc == source_inc) {
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op(destination_inc | MicroOp::SourceMask | MicroOp::DestinationMask);
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} else {
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op(destination_inc | MicroOp::DestinationMask);
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op(source_inc | MicroOp::SourceMask);
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}
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} break;
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} break;
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case Operation::CMPl:
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case Operation::CMPl:
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op( int(Action::CopyToEffectiveAddress) | MicroOp::SourceMask | MicroOp::DestinationMask,
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op( int(Action::CopyToEffectiveAddress) | MicroOp::SourceMask,
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seq("nR+ nr nRd+ nrd np", {ea(0), ea(0), ea(1), ea(1)}));
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seq("nR+ nr", {ea(0), ea(0)}));
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op(int(Action::Increment4) | MicroOp::SourceMask);
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op( int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask,
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seq("nRd+ nrd np", {ea(1), ea(1)}));
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op(int(Action::Increment4) | MicroOp::DestinationMask);
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op(Action::PerformOperation);
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op(Action::PerformOperation);
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op(int(Action::Increment4) | MicroOp::SourceMask | MicroOp::DestinationMask);
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break;
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break;
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}
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}
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} break;
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} break;
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