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https://github.com/TomHarte/CLK.git
synced 2025-04-09 00:37:27 +00:00
Started trying to wade back to passing tests. Working on the new timing tests first, and focussing on getting the Objective-C test machine to compile bus operations into machine cycles, which means indicating phase to all-RAM delegates.
This commit is contained in:
Thomas Harte
parent
cb140aa06e
commit
d668879ba6
@ -11,7 +11,11 @@
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#import "TestMachine+ForSubclassEyesOnly.h"
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@interface CSTestMachineZ80 ()
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- (void)testMachineDidPerformBusOperation:(CPU::Z80::MachineCycle::Operation)operation address:(uint16_t)address value:(uint8_t)value timeStamp:(int)time_stamp;
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- (void)testMachineDidPerformBusOperation:(CPU::Z80::MachineCycle::Operation)operation
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phase:(CPU::Z80::MachineCycle::Phase)phase
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address:(uint16_t)address
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value:(uint8_t)value
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timeStamp:(int)time_stamp;
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@end
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#pragma mark - C++ delegate handlers
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@ -20,8 +24,8 @@ class BusOperationHandler: public CPU::Z80::AllRAMProcessor::MemoryAccessDelegat
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public:
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BusOperationHandler(CSTestMachineZ80 *targetMachine) : target_(targetMachine) {}
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void z80_all_ram_processor_did_perform_bus_operation(CPU::Z80::AllRAMProcessor &processor, CPU::Z80::MachineCycle::Operation operation, uint16_t address, uint8_t value, int time_stamp) {
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[target_ testMachineDidPerformBusOperation:operation address:address value:value timeStamp:time_stamp];
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void z80_all_ram_processor_did_perform_bus_operation(CPU::Z80::AllRAMProcessor &processor, CPU::Z80::MachineCycle::Operation operation, CPU::Z80::MachineCycle::Phase phase, uint16_t address, uint8_t value, int time_stamp) {
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[target_ testMachineDidPerformBusOperation:operation phase:phase address:address value:value timeStamp:time_stamp];
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}
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private:
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@ -152,7 +156,7 @@ static CPU::Z80::Register registerForRegister(CSTestMachineZ80Register reg) {
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}
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- (int)completedCycles {
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return _processor->get_length_of_completed_machine_cycles();
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return _processor->get_timestamp();
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}
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- (void)setNmiLine:(BOOL)nmiLine {
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@ -187,7 +191,7 @@ static CPU::Z80::Register registerForRegister(CSTestMachineZ80Register reg) {
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_processor->set_memory_access_delegate(captureBusActivity ? _busOperationHandler : nullptr);
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}
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- (void)testMachineDidPerformBusOperation:(CPU::Z80::MachineCycle::Operation)operation address:(uint16_t)address value:(uint8_t)value timeStamp:(int)timeStamp {
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- (void)testMachineDidPerformBusOperation:(CPU::Z80::MachineCycle::Operation)operation phase:(CPU::Z80::MachineCycle::Phase)phase address:(uint16_t)address value:(uint8_t)value timeStamp:(int)timeStamp {
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int length = timeStamp - _lastOpcodeTime;
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_lastOpcodeTime = timeStamp;
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if(operation == CPU::Z80::MachineCycle::Operation::ReadOpcode && length < _timeSeekingReadOpcode)
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@ -195,39 +199,42 @@ static CPU::Z80::Register registerForRegister(CSTestMachineZ80Register reg) {
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if(self.captureBusActivity) {
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CSTestMachineZ80BusOperationCapture *capture = [[CSTestMachineZ80BusOperationCapture alloc] init];
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switch(operation) {
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case CPU::Z80::MachineCycle::Operation::Write:
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capture.operation = CSTestMachineZ80BusOperationCaptureOperationWrite;
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break;
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if(phase == CPU::Z80::MachineCycle::Phase::End) {
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switch(operation) {
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case CPU::Z80::MachineCycle::Operation::Write:
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capture.operation = CSTestMachineZ80BusOperationCaptureOperationWrite;
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break;
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case CPU::Z80::MachineCycle::Operation::Read:
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capture.operation = CSTestMachineZ80BusOperationCaptureOperationRead;
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break;
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case CPU::Z80::MachineCycle::Operation::Read:
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capture.operation = CSTestMachineZ80BusOperationCaptureOperationRead;
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break;
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case CPU::Z80::MachineCycle::Operation::ReadOpcode:
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capture.operation = CSTestMachineZ80BusOperationCaptureOperationReadOpcode;
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break;
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case CPU::Z80::MachineCycle::Operation::ReadOpcode:
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case CPU::Z80::MachineCycle::Operation::Refresh:
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capture.operation = CSTestMachineZ80BusOperationCaptureOperationReadOpcode;
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break;
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case CPU::Z80::MachineCycle::Operation::Input:
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capture.operation = CSTestMachineZ80BusOperationCaptureOperationPortRead;
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break;
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case CPU::Z80::MachineCycle::Operation::Input:
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capture.operation = CSTestMachineZ80BusOperationCaptureOperationPortRead;
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break;
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case CPU::Z80::MachineCycle::Operation::Output:
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capture.operation = CSTestMachineZ80BusOperationCaptureOperationPortWrite;
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break;
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case CPU::Z80::MachineCycle::Operation::Output:
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capture.operation = CSTestMachineZ80BusOperationCaptureOperationPortWrite;
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break;
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case CPU::Z80::MachineCycle::Operation::Internal:
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capture.operation = CSTestMachineZ80BusOperationCaptureOperationInternalOperation;
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break;
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case CPU::Z80::MachineCycle::Operation::Internal:
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capture.operation = CSTestMachineZ80BusOperationCaptureOperationInternalOperation;
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break;
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default:
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return;
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default:
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return;
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}
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capture.address = address;
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capture.value = value;
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capture.timeStamp = timeStamp;
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[_busOperationCaptures addObject:capture];
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}
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capture.address = address;
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capture.value = value;
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capture.timeStamp = timeStamp;
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[_busOperationCaptures addObject:capture];
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}
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}
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@ -86,7 +86,7 @@ struct MachineCycle {
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// Elemental bus operations
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#define ReadOpcodeStart(addr, val) {MachineCycle::ReadOpcode, MachineCycle::Phase::Start, 2, &addr.full, &val, false}
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#define ReadOpcodeWait(addr, val) {MachineCycle::ReadOpcode, MachineCycle::Phase::Wait, 1, &addr.full, &val, true}
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#define Refresh(len) {MachineCycle::Refresh, MachineCycle::Phase::Start, 2, &ir_.full, nullptr, false}
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#define Refresh(len) {MachineCycle::Refresh, MachineCycle::Phase::End, 2, &ir_.full, nullptr, false}
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#define ReadStart(addr, val) {MachineCycle::Read, MachineCycle::Phase::Start, 2, &addr.full, &val, false}
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#define ReadWait(l, addr, val, f) {MachineCycle::Read, MachineCycle::Phase::Wait, l, &addr.full, &val, f}
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@ -14,49 +14,47 @@ namespace {
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class ConcreteAllRAMProcessor: public AllRAMProcessor, public Processor<ConcreteAllRAMProcessor> {
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public:
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ConcreteAllRAMProcessor() : AllRAMProcessor(), completed_cycles(0) {}
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ConcreteAllRAMProcessor() : AllRAMProcessor() {}
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inline int perform_machine_cycle(const MachineCycle &cycle) {
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completed_cycles += cycle.length;
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uint16_t address = cycle.address ? *cycle.address : 0x0000;
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switch(cycle.operation) {
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case MachineCycle::Operation::ReadOpcode:
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// printf("! ");
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check_address_for_trap(address);
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case MachineCycle::Operation::Read:
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// printf("r %04x [%02x] AF:%04x BC:%04x DE:%04x HL:%04x SP:%04x\n", address, memory_[address], get_value_of_register(CPU::Z80::Register::AF), get_value_of_register(CPU::Z80::Register::BC), get_value_of_register(CPU::Z80::Register::DE), get_value_of_register(CPU::Z80::Register::HL), get_value_of_register(CPU::Z80::Register::StackPointer));
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*cycle.value = memory_[address];
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break;
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case MachineCycle::Operation::Write:
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// printf("w %04x\n", address);
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memory_[address] = *cycle.value;
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break;
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// if(cycle.phase == MachineCycle::Phase::End) {
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switch(cycle.operation) {
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case MachineCycle::Operation::ReadOpcode:
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check_address_for_trap(address);
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case MachineCycle::Operation::Read:
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*cycle.value = memory_[address];
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break;
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case MachineCycle::Operation::Write:
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memory_[address] = *cycle.value;
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break;
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case MachineCycle::Operation::Output:
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break;
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case MachineCycle::Operation::Input:
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// This logic is selected specifically because it seems to match
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// the FUSE unit tests. It might need factoring out.
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*cycle.value = address >> 8;
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break;
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case MachineCycle::Operation::Output:
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break;
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case MachineCycle::Operation::Input:
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// This logic is selected specifically because it seems to match
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// the FUSE unit tests. It might need factoring out.
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*cycle.value = address >> 8;
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break;
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case MachineCycle::Operation::Internal:
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break;
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case MachineCycle::Operation::Internal:
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break;
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case MachineCycle::Operation::Interrupt:
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// A pick that means LD HL, (nn) if interpreted as an instruction but is otherwise
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// arbitrary.
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*cycle.value = 0x21;
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break;
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case MachineCycle::Operation::Interrupt:
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// A pick that means LD HL, (nn) if interpreted as an instruction but is otherwise
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// arbitrary.
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*cycle.value = 0x21;
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break;
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default:
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printf("???\n");
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break;
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}
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default:
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printf("???\n");
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break;
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}
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// }
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timestamp_ += cycle.length;
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if(delegate_ != nullptr) {
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delegate_->z80_all_ram_processor_did_perform_bus_operation(*this, cycle.operation, address, cycle.value ? *cycle.value : 0x00, timestamp_);
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delegate_->z80_all_ram_processor_did_perform_bus_operation(*this, cycle.operation, cycle.phase, address, cycle.value ? *cycle.value : 0x00, timestamp_);
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}
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return 0;
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@ -89,14 +87,6 @@ class ConcreteAllRAMProcessor: public AllRAMProcessor, public Processor<Concrete
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void set_non_maskable_interrupt_line(bool value) {
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CPU::Z80::Processor<ConcreteAllRAMProcessor>::set_non_maskable_interrupt_line(value);
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}
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int get_length_of_completed_machine_cycles() {
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return completed_cycles;
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}
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private:
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int completed_cycles;
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};
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}
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@ -22,7 +22,7 @@ class AllRAMProcessor:
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static AllRAMProcessor *Processor();
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struct MemoryAccessDelegate {
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virtual void z80_all_ram_processor_did_perform_bus_operation(AllRAMProcessor &processor, MachineCycle::Operation operation, uint16_t address, uint8_t value, int time_stamp) = 0;
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virtual void z80_all_ram_processor_did_perform_bus_operation(CPU::Z80::AllRAMProcessor &processor, CPU::Z80::MachineCycle::Operation operation, CPU::Z80::MachineCycle::Phase phase, uint16_t address, uint8_t value, int time_stamp) = 0;
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};
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inline void set_memory_access_delegate(MemoryAccessDelegate *delegate) {
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delegate_ = delegate;
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@ -36,8 +36,6 @@ class AllRAMProcessor:
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virtual void set_interrupt_line(bool value) = 0;
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virtual void set_non_maskable_interrupt_line(bool value) = 0;
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virtual int get_length_of_completed_machine_cycles() = 0;
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protected:
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MemoryAccessDelegate *delegate_;
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AllRAMProcessor() : ::CPU::AllRAMProcessor(65536), delegate_(nullptr) {}
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