mirror of
https://github.com/TomHarte/CLK.git
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Switches to generators with stable pointers; adds 2a.
This commit is contained in:
Thomas Harte
parent
5c9192e5e6
commit
d707c5ac95
@ -6,20 +6,11 @@
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// Copyright © 2020 Thomas Harte. All rights reserved.
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//
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#include <cstdint>
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#include <vector>
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#include "../65816.hpp"
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#include "65816Storage.hpp"
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using namespace CPU::WDC65816;
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namespace {
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enum class AccessType {
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Read, Write, ReadModifyWrite
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};
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}
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ProcessorStorage::ProcessorStorage() {
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struct CPU::WDC65816::ProcessorStorageConstructor {
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/*
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Code below is structured to ease translation from Table 5-7 of the 2018
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edition of the WDC 65816 datasheet.
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@ -39,10 +30,10 @@ ProcessorStorage::ProcessorStorage() {
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*/
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// 1a. Absolute a.
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auto absolute = [] (AccessType type, bool is8bit, const std::function<void(MicroOp)> &target) {
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target(CycleFetchIncrementPC); // AAL.
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target(CycleFetchIncrementPC); // AAH.
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target(OperationConstructAbsolute); // Calculate data address.
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static void absolute(AccessType type, bool is8bit, const std::function<void(MicroOp)> &target) {
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target(CycleFetchIncrementPC); // AAL.
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target(CycleFetchIncrementPC); // AAH.
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target(OperationConstructAbsolute); // Calculate data address.
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if(type == AccessType::Write) {
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target(OperationPerform); // Perform operation to fill the data buffer.
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@ -56,27 +47,29 @@ ProcessorStorage::ProcessorStorage() {
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};
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// 1b. Absolute a, JMP.
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auto absolute_jmp = [] (AccessType, bool, const std::function<void(MicroOp)> &target) {
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static void absolute_jmp(AccessType, bool, const std::function<void(MicroOp)> &target) {
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target(CycleFetchIncrementPC); // New PCL.
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target(CycleFetchIncrementPC); // New PCH.
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target(CycleFetchPC); // New PCH.
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target(OperationConstructAbsolute); // Calculate data address.
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target(OperationPerform); // [JMP]
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};
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// 1c. Absolute a, JSR.
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auto absolute_jsr = [] (AccessType, bool, const std::function<void(MicroOp)> &target) {
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static void absolute_jsr(AccessType, bool, const std::function<void(MicroOp)> &target) {
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target(CycleFetchIncrementPC); // New PCL.
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target(CycleFetchIncrementPC); // New PCH.
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target(CycleFetchPCDiscard); // IO
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target(CycleFetchPC); // New PCH.
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target(CycleFetchPC); // IO
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target(OperationConstructAbsolute); // Calculate data address.
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target(OperationPerform); // [JSR]
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target(CyclePush); // PCH
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target(CyclePush); // PCL
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};
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// 1d. Absolute read-modify-write.
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auto absolute_rmw = [] (AccessType, bool is8bit, const std::function<void(MicroOp)> &target) {
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target(CycleFetchIncrementPC); // AAL.
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target(CycleFetchIncrementPC); // AAH.
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target(OperationConstructAbsolute); // Calculate data address.
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static void absolute_rmw(AccessType, bool is8bit, const std::function<void(MicroOp)> &target) {
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target(CycleFetchIncrementPC); // AAL.
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target(CycleFetchIncrementPC); // AAH.
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target(OperationConstructAbsolute); // Calculate data address.
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if(!is8bit) target(CycleFetchIncrementData); // Data low.
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target(CycleFetchData); // Data [high].
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@ -90,8 +83,57 @@ ProcessorStorage::ProcessorStorage() {
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target(CycleStoreData); // Data [low].
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};
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// 2a. Absolute Indexed Indirect (a, x), JMP.
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static void absolute_indexed_indirect_jmp(AccessType, bool, const std::function<void(MicroOp)> &target) {
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target(CycleFetchIncrementPC); // AAL.
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target(CycleFetchPC); // AAH.
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target(CycleFetchPC); // IO.
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target(OperationConstructAbsoluteIndexedIndirect); // Calculate data address.
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target(CycleFetchIncrementData); // New PCL
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target(CycleFetchData); // New PCH.
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target(OperationPerform); // [JMP]
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};
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// 2b. Absolute Indexed Indirect (a, x), JSR.
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};
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AccessType ProcessorStorage::access_type_for_operation(Operation operation) {
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switch(operation) {
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case ADC: case AND: case BIT: case CMP:
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case CPX: case CPY: case EOR: case ORA:
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case SBC:
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case LDA: case LDX: case LDY:
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case JMP: case JSR:
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return AccessType::Read;
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case STA: case STX: case STY: case STZ:
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return AccessType::Write;
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}
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}
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void ProcessorStorage::install(void (* generator)(AccessType, bool, const std::function<void(MicroOp)>&), Operation operation, ProcessorStorageConstructor &) {
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const AccessType access_type = access_type_for_operation(operation);
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(*generator)(access_type, true, [] (MicroOp) {});
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// TODO:
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// (1) use [hash of] pointer to generator to determine whether operation tables have already been built;
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// (2) if not, build them in both 8- and 16-bit variations;
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// (3) insert appropriate entries into an instruction table for the current instruction; and
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// (4) increment the instruction counter.
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//
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// Additional observation: temporary storage would be helpful, so load that into ProcessorStorageConstructor.
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}
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ProcessorStorage::ProcessorStorage() {
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ProcessorStorageConstructor constructor;
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// Install the instructions.
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#define op set_instruction
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#define op(x, y) install(&ProcessorStorageConstructor::x, y, constructor)
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/* 0x00 BRK s */
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/* 0x01 ORA (d, x) */
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/* 0x02 COP s */
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@ -105,7 +147,7 @@ ProcessorStorage::ProcessorStorage() {
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/* 0x0a ASL a */
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/* 0x0b PHD s */
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/* 0x0c TSB a */
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/* 0x0d ORA a */ // op(0x0d, absolute_read, ORA);
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/* 0x0d ORA a */ op(absolute, ORA);
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/* 0x0e ASL a */
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/* 0x0f ORA al */
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@ -126,7 +168,7 @@ ProcessorStorage::ProcessorStorage() {
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/* 0x1e ASL a, x */
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/* 0x1f ORA al, x */
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/* 0x20 JSR a */ // op(0x20, absolute_jsr, JSR);
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/* 0x20 JSR a */ op(absolute_jsr, JSR);
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/* 0x21 ORA (d), y */
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/* 0x22 AND (d, x) */
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/* 0x23 JSL al */
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@ -138,8 +180,8 @@ ProcessorStorage::ProcessorStorage() {
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/* 0x29 AND # */
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/* 0x2a ROL A */
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/* 0x2b PLD s */
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/* 0x2c BIT a */ // op(0x2c, absolute_read, BIT);
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/* 0x2d AND a */ // op(0x2d, absolute_read, AND);
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/* 0x2c BIT a */ op(absolute, BIT);
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/* 0x2d AND a */ op(absolute, AND);
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/* 0x2e ROL a */
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/* 0x2f AND al */
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@ -172,8 +214,8 @@ ProcessorStorage::ProcessorStorage() {
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/* 0x49 EOR # */
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/* 0x4a LSR A */
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/* 0x4b PHK s */
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/* 0x4c JMP a */ // op(0x4c, absolute_jmp, JMP);
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/* 0x4d EOR a */ // op(0x4d, absolute_read, EOR);
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/* 0x4c JMP a */ op(absolute, JMP);
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/* 0x4d EOR a */ op(absolute, EOR);
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/* 0x4e LSR a */
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/* 0x4f EOR Al */
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@ -207,7 +249,7 @@ ProcessorStorage::ProcessorStorage() {
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/* 0x6a ROR A */
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/* 0x6b RTL s */
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/* 0x6c JMP (a) */
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/* 0x6d ADC a */ // op(0x6d, absolute_read, ADC);
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/* 0x6d ADC a */ op(absolute, ADC);
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/* 0x6e ROR a */
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/* 0x6f ADC al */
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@ -223,7 +265,7 @@ ProcessorStorage::ProcessorStorage() {
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/* 0x79 ADC a, y */
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/* 0x7a PLY s */
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/* 0x7b TDC i */
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/* 0x7c JMP (a, x) */
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/* 0x7c JMP (a, x) */ op(absolute_indexed_indirect_jmp, JMP);
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/* 0x7d ADC a, x */
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/* 0x7e ROR a, x */
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/* 0x7f ADC al, x */
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@ -240,9 +282,9 @@ ProcessorStorage::ProcessorStorage() {
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/* 0x89 BIT # */
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/* 0x8a TXA i */
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/* 0x8b PHB s */
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/* 0x8c STY a */ // op(0x8c, absolute_write, STY);
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/* 0x8d STA a */ // op(0x8d, absolute_write, STA);
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/* 0x8e STX a */ // op(0x8e, absolute_write, STX);
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/* 0x8c STY a */ op(absolute, STY);
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/* 0x8d STA a */ op(absolute, STA);
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/* 0x8e STX a */ op(absolute, STX);
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/* 0x8f STA al */
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/* 0x90 BCC r */
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@ -257,7 +299,7 @@ ProcessorStorage::ProcessorStorage() {
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/* 0x99 STA a, y */
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/* 0x9a TXS i */
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/* 0x9b TXY i */
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/* 0x9c STZ a */ // op(0x9c, absolute_write, STZ);
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/* 0x9c STZ a */ op(absolute, STZ);
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/* 0x9d STA a, x */
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/* 0x9e STZ a, x */
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/* 0x9f STA al, x */
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@ -274,9 +316,9 @@ ProcessorStorage::ProcessorStorage() {
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/* 0xa9 LDA # */
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/* 0xaa TAX i */
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/* 0xab PLB s */
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/* 0xac LDY a */ // op(0xac, absolute_read, LDY);
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/* 0xad LDA a */ // op(0xad, absolute_read, LDA);
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/* 0xae LDX a */ // op(0xae, absolute_read, LDX);
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/* 0xac LDY a */ op(absolute, LDY);
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/* 0xad LDA a */ op(absolute, LDA);
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/* 0xae LDX a */ op(absolute, LDX);
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/* 0xaf LDA al */
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/* 0xb0 BCS r */
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@ -308,8 +350,8 @@ ProcessorStorage::ProcessorStorage() {
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/* 0xc9 CMP # */
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/* 0xca DEX i */
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/* 0xcb WAI i */
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/* 0xcc CPY a */ // op(0xcd, absolute_read, CPY);
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/* 0xcd CMP a */ // op(0xcd, absolute_read, CMP);
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/* 0xcc CPY a */ op(absolute, CPY);
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/* 0xcd CMP a */ op(absolute, CMP);
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/* 0xce DEC a */
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/* 0xcf CMP al */
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@ -342,8 +384,8 @@ ProcessorStorage::ProcessorStorage() {
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/* 0xe9 SBC # */
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/* 0xea NOP i */
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/* 0xeb XBA i */
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/* 0xec CPX a */ // op(0xec, absolute_read, CPX);
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/* 0xed SBC a */ // op(0xed, absolute_read, SBC);
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/* 0xec CPX a */ op(absolute, CPX);
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/* 0xed SBC a */ op(absolute, SBC);
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/* 0xee INC a */
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/* 0xef SBC al */
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@ -9,56 +9,67 @@
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#ifndef WDC65816Implementation_h
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#define WDC65816Implementation_h
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enum MicroOp: uint8_t {
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/// Fetches a byte from the program counter to the instruction buffer and increments the program counter.
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CycleFetchIncrementPC,
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/// Fetches a byte from the program counter without incrementing it, and throws it away.
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CycleFetchPC,
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/// Fetches a byte from the data address to the data buffer.
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CycleFetchData,
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/// Fetches a byte from the data address to the data buffer and increments the data address.
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CycleFetchIncrementData,
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/// Stores a byte from the data buffer.
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CycleStoreData,
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/// Stores a byte to the data address from the data buffer and increments the data address.
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CycleStoreIncrementData,
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/// Stores a byte to the data address from the data buffer and decrements the data address.
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CycleStoreDecrementData,
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/// Pushes a single byte from the data buffer to the stack.
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CyclePush,
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/// Sets the data address by copying the final two bytes of the instruction buffer.
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OperationConstructAbsolute,
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/// Sets the data address
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OperationConstructAbsoluteIndexedIndirect,
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/// Performs whatever operation goes with this program.
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OperationPerform,
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/// Complete this set of micr-ops.
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OperationMoveToNextProgram
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};
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enum class AccessType {
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Read, Write
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};
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class ProcessorStorageConstructor;
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class ProcessorStorage {
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public:
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ProcessorStorage();
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enum MicroOp: uint8_t {
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/// Fetches a byte from the program counter to the instruction buffer and increments the program counter.
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CycleFetchIncrementPC,
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/// Fetches a byte from the program counter without incrementing it, and throws it away.
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CycleFetchPCDiscard,
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/// Fetches a byte from the data address to the data buffer.
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CycleFetchData,
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/// Fetches a byte from the data address to the data buffer and increments the data address.
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CycleFetchIncrementData,
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/// Stores a byte from the data buffer.
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CycleStoreData,
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/// Stores a byte to the data address from the data buffer and increments the data address.
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CycleStoreIncrementData,
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/// Stores a byte to the data address from the data buffer and decrements the data address.
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CycleStoreDecrementData,
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/// Pushes a single byte from the data buffer to the stack.
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CyclePush,
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/// Sets the data address by copying the final two bytes of the instruction buffer.
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OperationConstructAbsolute,
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/// Performs whatever operation goes with this program.
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OperationPerform,
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/// Complete this set of micr-ops.
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OperationMoveToNextProgram
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};
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enum Operation: uint8_t {
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// These perform the named operation using the value in the data buffer.
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// These perform the named operation using the value in the data buffer;
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// they are implicitly AccessType::Read.
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ADC, AND, BIT, CMP, CPX, CPY, EOR, ORA, SBC,
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// These load the respective register from the data buffer.
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// These load the respective register from the data buffer;
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// they are implicitly AccessType::Read.
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LDA, LDX, LDY,
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// These move the respective register (or value) to the data buffer.
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// These move the respective register (or value) to the data buffer;
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// they are implicitly AccessType::Write.
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STA, STX, STY, STZ,
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/// Loads the PC with the operand from the instruction buffer.
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/// Loads the PC with the operand from the data buffer.
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JMP,
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/// Loads the PC with the operand from the instruction buffer, placing
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/// the old PC into the data buffer.
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/// Loads the PC with the operand from the daa buffer, replacing
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/// it with the old PC.
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JSR,
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};
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@ -71,17 +82,8 @@ class ProcessorStorage {
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private:
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std::vector<MicroOp> micro_ops_;
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size_t install_ops(std::initializer_list<MicroOp> ops) {
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// Just copy into place and return the index at which copying began.
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const size_t index = micro_ops_.size();
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micro_ops_.insert(micro_ops_.end(), ops.begin(), ops.end());
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return index;
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}
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void set_instruction(uint8_t opcode, size_t micro_ops, Operation operation) {
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instructions[opcode].program_offset = micro_ops;
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instructions[opcode].operation = operation;
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}
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AccessType access_type_for_operation(Operation);
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void install(void (* generator)(AccessType, bool, const std::function<void(MicroOp)>&), Operation, ProcessorStorageConstructor &);
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};
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#endif /* WDC65816Implementation_h */
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