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Adds test for MOVEA.w (0x1000), A1 and fixes implementation thereof.
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@ -124,7 +124,9 @@ class RAM68000: public CPU::MC68000::BusHandler {
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_machine->set_program({
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0x303c, 0xfb2e, // MOVE #fb2e, D0
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0x3200, // MOVE D0, D1
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0x3040, // MOVE D0, A0
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0x3040, // MOVEA D0, A0
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0x3278, 0x0400, // MOVEA.w (0x0400), A1
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});
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// Perform RESET.
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@ -142,10 +144,15 @@ class RAM68000: public CPU::MC68000::BusHandler {
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state = _machine->get_processor_state();
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XCTAssert(state.data[1] == 0xfb2e);
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// Perform MOVE D0, A0
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// Perform MOVEA D0, A0
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_machine->run_for(Cycles(4));
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state = _machine->get_processor_state();
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XCTAssert(state.address[0] == 0xfffffb2e, "A0 was %08x instead of 0xfffffb2e", state.address[0]);
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// Perform MOVEA.w (0x1000), A1
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_machine->run_for(Cycles(13));
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state = _machine->get_processor_state();
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XCTAssert(state.address[1] == 0x0000303c, "A1 was %08x instead of 0x0000303c", state.address[1]);
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}
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@end
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@ -239,11 +239,12 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
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#undef CalculateD8AnXn
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case int(MicroOp::Action::AssembleWordFromPrefetch) | MicroOp::SourceMask:
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effective_address_[0] = prefetch_queue_.halves.high.full;
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// Assumption: this will be assembling right at the start of the instruction.
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effective_address_[0] = prefetch_queue_.halves.low.full;
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break;
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case int(MicroOp::Action::AssembleWordFromPrefetch) | MicroOp::DestinationMask:
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effective_address_[1] = prefetch_queue_.halves.high.full;
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effective_address_[1] = prefetch_queue_.halves.low.full;
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break;
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case int(MicroOp::Action::AssembleLongWordFromPrefetch) | MicroOp::SourceMask:
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@ -387,14 +387,14 @@ struct ProcessorStorageConstructor {
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} else {
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op();
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}
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continue;
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break;
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case 0x0004: // MOVE Dn, -(An)
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case 0x0104: // MOVE An, -(An)
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op( int(is_byte_access ? Action::Decrement1 : Action::Decrement2) | MicroOp::DestinationMask,
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seq("np nw", { &storage_.address_[destination_register].full }, !is_byte_access));
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op(is_byte_access ? Action::SetMoveFlagsb : Action::SetMoveFlagsw);
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continue;
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break;
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case 0x0005: // MOVE Dn, (d16, An)
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case 0x0105: // MOVE An, (d16, An)
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@ -562,12 +562,14 @@ struct ProcessorStorageConstructor {
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// Source = (xxx).W
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//
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case 0x1001: // MOVEA (xxx).W, Dn
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case 0x1001: // MOVEA (xxx).W, An
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operation = Operation::MOVEAw;
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case 0x1000: // MOVE (xxx).W, Dn
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op(int(MicroOp::Action::AssembleWordFromPrefetch) | MicroOp::SourceMask, seq("np"));
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op(Action::PerformOperation, seq("nr np", { &storage_.effective_address_[0] }, !is_byte_access));
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continue;
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op(
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int(MicroOp::Action::AssembleWordFromPrefetch) | MicroOp::SourceMask,
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seq("np nr np", { &storage_.effective_address_[0] }, !is_byte_access));
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op(Action::PerformOperation);
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break;
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case 0x1002: // MOVE (xxx).W, (An)
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case 0x1003: // MOVE (xxx).W, (An)+
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@ -603,7 +605,8 @@ struct ProcessorStorageConstructor {
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case 0x1100: // MOVE (xxx).W, Dn
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op(int(MicroOp::Action::AssembleWordFromPrefetch) | MicroOp::SourceMask, seq("np np"));
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op(Action::PerformOperation, seq("nr np", { &storage_.effective_address_[0] }, !is_byte_access));
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continue;
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op();
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break;
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//
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// Source = (d16, PC)
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@ -640,11 +643,10 @@ struct ProcessorStorageConstructor {
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//
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default:
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std::cerr << "Unimplemented MOVE " << std::hex << both_modes << std::endl;
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std::cerr << "Unimplemented MOVE " << std::hex << both_modes << " " << instruction << std::endl;
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// TODO: all other types of mode.
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continue;
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}
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}
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} break;
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