6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-12-26 09:29:45 +00:00
Code Issues Projects Releases Wiki Activity

Reduced 1540 PLL to running at 4Mhz. Which is possibly correct (?) Made minor change to avoid divide if possible.

Browse Source
This commit is contained in:
Thomas Harte 2016-08-02 21:28:50 -04:00
parent 5d40d70c92
commit d832e5e10d
2 changed files with 4 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Machines/Commodore/1540/C1540.cpp
View File

@ -14,7 +14,7 @@ using namespace Commodore::C1540;
Machine::Machine() :
_shift_register(0),
Storage::DiskDrive(1000000, 16, 300)
Storage::DiskDrive(1000000, 4, 300)
{
// create a serial port and a VIA to run it
_serialPortVIA.reset(new SerialPortVIA);

5
Storage/Disk/DigitalPhaseLockedLoop.cpp
View File

@ -27,9 +27,10 @@ DigitalPhaseLockedLoop::DigitalPhaseLockedLoop(int clocks_per_bit, int tolerance
void DigitalPhaseLockedLoop::run_for_cycles(int number_of_cycles)
{
_phase += number_of_cycles;
int windows_crossed = _phase / _window_length;
if(windows_crossed)
if(_phase >= _window_length)
{
int windows_crossed = _phase / _window_length;
// check whether this triggers any 0s, if anybody cares
if(_delegate)
{