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https://github.com/TomHarte/CLK.git
synced 2024-09-06 20:54:31 +00:00
Fixes: switched ZX80 and ZX81 timing to the correct way around, ensured that my wait takes effect if HALT **isn't** set, and made sure to recover from it.
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@ -38,12 +38,12 @@ int Machine::perform_machine_cycle(const CPU::Z80::MachineCycle &cycle) {
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set_hsync(true);
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set_hsync(true);
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if(nmi_is_enabled_) {
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if(nmi_is_enabled_) {
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set_non_maskable_interrupt_line(true);
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set_non_maskable_interrupt_line(true);
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if(get_halt_line()) {
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if(!get_halt_line()) {
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wait_cycles = vsync_start_cycle_ - horizontal_counter_;
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wait_cycles = vsync_end_cycle_ - horizontal_counter_;
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}
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}
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}
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}
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video_->run_for_cycles(horizontal_counter_ - vsync_start_cycle_ + wait_cycles);
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video_->run_for_cycles(horizontal_counter_ - vsync_start_cycle_ + wait_cycles);
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} else if(previous_counter < vsync_end_cycle_ && horizontal_counter_ >= vsync_end_cycle_) {
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} else if(previous_counter <= vsync_end_cycle_ && horizontal_counter_ > vsync_end_cycle_) {
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video_->run_for_cycles(vsync_end_cycle_ - previous_counter);
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video_->run_for_cycles(vsync_end_cycle_ - previous_counter);
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set_hsync(false);
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set_hsync(false);
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if(nmi_is_enabled_) set_non_maskable_interrupt_line(false);
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if(nmi_is_enabled_) set_non_maskable_interrupt_line(false);
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@ -180,12 +180,14 @@ void Machine::configure_as_target(const StaticAnalyser::Target &target) {
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tape_return_address_ = 0x380;
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tape_return_address_ = 0x380;
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vsync_start_cycle_ = 13;
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vsync_start_cycle_ = 13;
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vsync_end_cycle_ = 33;
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vsync_end_cycle_ = 33;
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vsync_start_cycle_ = 16;
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vsync_end_cycle_ = 32;
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} else {
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} else {
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rom_ = zx80_rom_;
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rom_ = zx80_rom_;
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tape_trap_address_ = 0x220;
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tape_trap_address_ = 0x220;
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tape_return_address_ = 0x248;
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tape_return_address_ = 0x248;
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vsync_start_cycle_ = 16;
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vsync_start_cycle_ = 13;
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vsync_end_cycle_ = 32;
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vsync_end_cycle_ = 33;
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}
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}
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rom_mask_ = (uint16_t)(rom_.size() - 1);
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rom_mask_ = (uint16_t)(rom_.size() - 1);
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