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Introduces BSET tests, fixes BSET timing.

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This commit is contained in:
Thomas Harte 2019-06-23 22:53:37 -04:00
parent d50fbfb506
commit db4ca746e3
2 changed files with 45 additions and 1 deletions
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44
OSBindings/Mac/Clock SignalTests/68000Tests.mm
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@ -881,6 +881,50 @@ class CPU::MC68000::ProcessorStorageTests {
XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::ConditionCodes); XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::ConditionCodes);
} }
// MARK: BSET
- (void)performBSETD0D1:(uint32_t)d1 {
_machine->set_program({
0x03c0 // BSET D1, D0
});
auto state = _machine->get_processor_state();
state.data[0] = 0x12345678;
state.data[1] = d1;
_machine->set_processor_state(state);
_machine->run_for_instructions(1);
state = _machine->get_processor_state();
XCTAssertEqual(state.data[1], d1);
}
- (void)testBSET_D0D1_0 {
[self performBSETD0D1:0];
const auto state = _machine->get_processor_state();
XCTAssertEqual(state.data[0], 0x12345679);
XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
XCTAssertEqual(_machine->get_cycle_count(), 6);
}
- (void)testBSET_D0D1_10 {
[self performBSETD0D1:10];
const auto state = _machine->get_processor_state();
XCTAssertEqual(state.data[0], 0x12345678);
XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
XCTAssertEqual(_machine->get_cycle_count(), 6);
}
- (void)testBSET_D0D1_49 {
[self performBSETD0D1:49];
const auto state = _machine->get_processor_state();
XCTAssertEqual(state.data[0], 0x12365678);
XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
XCTAssertEqual(_machine->get_cycle_count(), 8);
}
// MARK: DBcc // MARK: DBcc
- (void)performDBccTestOpcode:(uint16_t)opcode status:(uint16_t)status d2Outcome:(uint32_t)d2Output { - (void)performDBccTestOpcode:(uint16_t)opcode status:(uint16_t)status d2Outcome:(uint32_t)d2Output {

2
Processors/68000/Implementation/68000Implementation.hpp
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@ -640,7 +640,7 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
case Operation::BSETl: case Operation::BSETl:
zero_result_ = active_program_->destination->full & (1 << (active_program_->source->full & 31)); zero_result_ = active_program_->destination->full & (1 << (active_program_->source->full & 31));
active_program_->destination->full |= 1 << (active_program_->source->full & 31); active_program_->destination->full |= 1 << (active_program_->source->full & 31);
active_step_->microcycle.length = HalfCycles(4 + (((active_program_->source->full & 31) / 16) * 4)); bus_program->microcycle.length = HalfCycles(4 + (((active_program_->source->full & 31) / 16) * 4));
break; break;
case Operation::BSETb: case Operation::BSETb: