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https://github.com/TomHarte/CLK.git
synced 2025-04-12 20:37:11 +00:00
Found and fixed some timing errors in absolute indexed and in (indirect), y addressing modes: neither is able in write or read-modify-write modes to shave a cycle as then can when reading.
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975836c30f
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@ -13,9 +13,9 @@ class TimingTests: XCTestCase, CSTestMachineJamHandler {
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private var endTime: UInt32 = 0
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func testImpliedNOP() {
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let code: [UInt8] = [0xea, CSTestMachineJamOpcode]
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self.runTest(code, expectedRunLength: 2)
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func testImplied() {
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let code: [UInt8] = [0xea, 0x88, 0xca, CSTestMachineJamOpcode]
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self.runTest(code, expectedRunLength: 6)
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}
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func testLDA() {
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@ -35,6 +35,33 @@ class TimingTests: XCTestCase, CSTestMachineJamHandler {
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self.runTest(code, expectedRunLength: 48)
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}
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func testSTA() {
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let code: [UInt8] = [
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0x85, 0x00, // [3] STA $00
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0x95, 0x00, // [4] STA $00,X
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0x8d, 0x00, 0x00, // [4] STA $0000
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0x9d, 0x00, 0x00, // [5] STA $0000, x (no wrap)
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0x9d, 0x02, 0x00, // [5] STA $0002, x (wrap)
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0x99, 0x00, 0x00, // [5] STA $0000, y (no wrap)
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0x99, 0x10, 0x00, // [5] STA $0010, y (wrap)
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0x81, 0x44, // [6] STA ($44, x)
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0x91, 0x00, // [6] STA ($00), y (no wrap)
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0x91, 0x02, // [6] STA ($01), y (wrap)
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CSTestMachineJamOpcode]
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self.runTest(code, expectedRunLength: 49)
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}
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func testINC() {
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let code: [UInt8] = [
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0xe6, 0x00, // [5] INC $00
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0xf6, 0x00, // [6] INC $00,X
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0xee, 0x00, 0x00, // [6] INC $0000
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0xfe, 0x00, 0x00, // [7] INC $0000, x (no wrap)
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0xfe, 0x02, 0x00, // [7] INC $0002, x (wrap)
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CSTestMachineJamOpcode]
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self.runTest(code, expectedRunLength: 31)
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}
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func testBCS() {
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let code: [UInt8] = [
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0x18, // [2] CLC
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@ -70,6 +97,14 @@ class TimingTests: XCTestCase, CSTestMachineJamHandler {
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self.runTest(code, expectedRunLength: 9)
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}
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func testSnippet2() {
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let code: [UInt8] = [
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0x16, 0x16, // [6] ASL $16, x
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0x46, 0x46, // [5] LSR $46
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CSTestMachineJamOpcode]
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self.runTest(code, expectedRunLength: 11)
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}
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func runTest(code: [UInt8], expectedRunLength: UInt32) {
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let machine = CSTestMachine()
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@ -63,7 +63,8 @@ template <class T> class Processor {
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CycleReadAndIncrementPC, CycleIncrementPCAndReadStack, CycleIncrementPCReadPCHLoadPCL, CycleReadPCHLoadPCL,
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CycleReadAddressHLoadAddressL, CycleReadPCLFromAddress, CycleReadPCHFromAddress, CycleLoadAddressAbsolute,
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OperationLoadAddressZeroPage, CycleLoadAddessZeroX, CycleLoadAddessZeroY, CycleAddXToAddressLow,
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CycleAddYToAddressLow, OperationCorrectAddressHigh, OperationMoveToNextProgram, OperationIncrementPC,
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CycleAddYToAddressLow, CycleAddXToAddressLowRead, OperationCorrectAddressHigh, CycleAddYToAddressLowRead,
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OperationMoveToNextProgram, OperationIncrementPC,
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CycleFetchOperandFromAddress, CycleWriteOperandToAddress, OperationCopyOperandFromA, OperationCopyOperandToA,
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CycleIncrementPCFetchAddressLowFromOperand, CycleAddXToOperandFetchAddressLow, CycleIncrementOperandFetchAddressHigh, OperationDecrementOperand,
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OperationIncrementOperand, OperationORA, OperationAND, OperationEOR,
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@ -137,26 +138,29 @@ template <class T> class Processor {
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#define Program(...) {__VA_ARGS__, OperationMoveToNextProgram}
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#define Absolute CycleLoadAddressAbsolute
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#define AbsoluteX CycleLoadAddressAbsolute, CycleAddXToAddressLow, OperationCorrectAddressHigh
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#define AbsoluteY CycleLoadAddressAbsolute, CycleAddYToAddressLow, OperationCorrectAddressHigh
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#define AbsoluteXr CycleLoadAddressAbsolute, CycleAddXToAddressLow, OperationCorrectAddressHigh
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#define AbsoluteYr CycleLoadAddressAbsolute, CycleAddYToAddressLow, OperationCorrectAddressHigh
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#define AbsoluteX CycleLoadAddressAbsolute, CycleAddXToAddressLowRead, OperationCorrectAddressHigh
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#define AbsoluteY CycleLoadAddressAbsolute, CycleAddYToAddressLowRead, OperationCorrectAddressHigh
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#define Zero OperationLoadAddressZeroPage
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#define ZeroX CycleLoadAddessZeroX
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#define ZeroY CycleLoadAddessZeroY
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#define IndexedIndirect CycleIncrementPCFetchAddressLowFromOperand, CycleAddXToOperandFetchAddressLow, CycleIncrementOperandFetchAddressHigh
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#define IndirectIndexed CycleIncrementPCFetchAddressLowFromOperand, CycleIncrementOperandFetchAddressHigh, CycleAddYToAddressLow, OperationCorrectAddressHigh
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#define IndirectIndexedr CycleIncrementPCFetchAddressLowFromOperand, CycleIncrementOperandFetchAddressHigh, CycleAddYToAddressLow, OperationCorrectAddressHigh
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#define IndirectIndexed CycleIncrementPCFetchAddressLowFromOperand, CycleIncrementOperandFetchAddressHigh, CycleAddYToAddressLowRead, OperationCorrectAddressHigh
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#define Read(op) CycleFetchOperandFromAddress, op
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#define Write(op) op, CycleWriteOperandToAddress
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#define ReadModifyWrite(...) CycleFetchOperandFromAddress, CycleWriteOperandToAddress, __VA_ARGS__, CycleWriteOperandToAddress
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#define AbsoluteRead(op) Program(Absolute, Read(op))
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#define AbsoluteXRead(op) Program(AbsoluteX, Read(op))
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#define AbsoluteYRead(op) Program(AbsoluteY, Read(op))
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#define AbsoluteXRead(op) Program(AbsoluteXr, Read(op))
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#define AbsoluteYRead(op) Program(AbsoluteYr, Read(op))
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#define ZeroRead(op) Program(Zero, Read(op))
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#define ZeroXRead(op) Program(ZeroX, Read(op))
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#define ZeroYRead(op) Program(ZeroY, Read(op))
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#define IndexedIndirectRead(op) Program(IndexedIndirect, Read(op))
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#define IndirectIndexedRead(op) Program(IndirectIndexed, Read(op))
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#define IndirectIndexedRead(op) Program(IndirectIndexedr, Read(op))
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#define AbsoluteWrite(op) Program(Absolute, Write(op))
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#define AbsoluteXWrite(op) Program(AbsoluteX, Write(op))
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@ -745,6 +749,11 @@ template <class T> class Processor {
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throwaway_read(_address.full);
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}
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break;
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case CycleAddXToAddressLowRead:
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_nextAddress.full = _address.full + _x;
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_address.bytes.low = _nextAddress.bytes.low;
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throwaway_read(_address.full);
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break;
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case CycleAddYToAddressLow:
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_nextAddress.full = _address.full + _y;
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_address.bytes.low = _nextAddress.bytes.low;
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@ -752,6 +761,11 @@ template <class T> class Processor {
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throwaway_read(_address.full);
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}
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break;
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case CycleAddYToAddressLowRead:
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_nextAddress.full = _address.full + _y;
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_address.bytes.low = _nextAddress.bytes.low;
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throwaway_read(_address.full);
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break;
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case OperationCorrectAddressHigh:
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_address.full = _nextAddress.full;
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break;
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