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Add B page and a large chunk of 4.
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Thomas Harte
parent
21ac9363e9
commit
dd5bdd67d7
@ -8,6 +8,8 @@
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#include "Decoder.hpp"
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#include <cassert>
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using namespace InstructionSet::M68k;
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namespace {
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@ -121,11 +123,111 @@ template <Operation operation> Preinstruction Predecoder::decode(uint16_t instru
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ea_combined_mode, ea_register,
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AddressingMode::DataRegisterDirect, data_register);
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default:
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// Should be unreachable.
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assert(false);
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}
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}
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// MARK: - Page decoders.
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Preinstruction Predecoder::decode4(uint16_t instruction) {
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switch(instruction & 0xfff) {
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case 0xe70: return decode<Operation::RESET>(instruction); // 6-83 (p537)
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case 0xe71: return decode<Operation::NOP>(instruction); // 8-13 (p469)
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case 0xe73: return decode<Operation::RTE>(instruction); // 6-84 (p538)
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case 0xe75: return decode<Operation::RTS>(instruction); // 4-169 (p273)
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case 0xe76: return decode<Operation::TRAPV>(instruction); // 4-191 (p295)
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case 0xe77: return decode<Operation::RTR>(instruction); // 4-168 (p272)
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default: break;
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}
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switch(instruction & 0xfc0) {
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// 4-146 (p250)
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case 0x000: return decode<Operation::NEGXb>(instruction);
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case 0x040: return decode<Operation::NEGXw>(instruction);
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case 0x080: return decode<Operation::NEGXl>(instruction);
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// 6-17 (p471)
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case 0x0c0: return decode<Operation::MOVEfromSR>(instruction);
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// 4-73 (p177)
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case 0x200: return decode<Operation::CLRb>(instruction);
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case 0x240: return decode<Operation::CLRw>(instruction);
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case 0x280: return decode<Operation::CLRl>(instruction);
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// 4-144 (p248)
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case 0x400: return decode<Operation::NEGb>(instruction);
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case 0x440: return decode<Operation::NEGw>(instruction);
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case 0x480: return decode<Operation::NEGl>(instruction);
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// 4-123 (p227)
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case 0x4c0: return decode<Operation::MOVEtoCCR>(instruction);
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// 4-148 (p250)
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case 0x600: return decode<Operation::NOTb>(instruction);
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case 0x640: return decode<Operation::NOTw>(instruction);
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case 0x680: return decode<Operation::NOTl>(instruction);
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// 4-123 (p227)
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case 0x6c0: return decode<Operation::MOVEtoSR>(instruction);
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// 4-142 (p246)
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case 0x800: return decode<Operation::NBCD>(instruction);
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// 4-159 (p263)
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case 0x840: return decode<Operation::PEA>(instruction);
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// 4-128 (p232)
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case 0x880: return decode<Operation::MOVEMtoMw>(instruction);
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case 0x8c0: return decode<Operation::MOVEMtoMl>(instruction);
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case 0xc80: return decode<Operation::MOVEMtoRw>(instruction);
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case 0xcc0: return decode<Operation::MOVEMtoRl>(instruction);
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// 4-192 (p296)
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case 0xa00: return decode<Operation::TSTb>(instruction);
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case 0xa40: return decode<Operation::TSTw>(instruction);
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case 0xa80: return decode<Operation::TSTl>(instruction);
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// 4-186 (p290)
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case 0xac0: return decode<Operation::TAS>(instruction);
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// 4-109 (p213)
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case 0xe80: return decode<Operation::JSR>(instruction);
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// 4-108 (p212)
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case 0xec0: return decode<Operation::JMP>(instruction);
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default: break;
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}
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switch(instruction & 0x1c0) {
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case 0x1c0: return decode<Operation::MOVEAl>(instruction); // 4-110 (p214)
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case 0x180: return decode<Operation::CHK>(instruction); // 4-69 (p173)
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default: break;
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}
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switch(instruction & 0xff0) {
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case 0xe40: return decode<Operation::TRAP>(instruction); // 4-188 (p292)
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// case 0xe60: return decode<Operation::MOVEtoUSP>(instruction); // 6-21 (p475)
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default: break;
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}
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// TODO: determine MOVEtoUSP and MOVEfromUSP.
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switch(instruction & 0xff8) {
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case 0xe60: return decode<Operation::SWAP>(instruction); // 4-185 (p289)
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case 0x880: return decode<Operation::EXTbtow>(instruction); // 4-106 (p210)
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case 0x8c0: return decode<Operation::EXTwtol>(instruction); // 4-106 (p210)
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case 0xe50: return decode<Operation::LINK>(instruction); // 4-111 (p215)
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case 0xe58: return decode<Operation::UNLINK>(instruction); // 4-194 (p298)
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default: break;
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}
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return Preinstruction();
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}
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Preinstruction Predecoder::decode8(uint16_t instruction) {
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// 4-171 (p275)
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if((instruction & 0x1f0) == 0x100) return decode<Operation::SBCD>(instruction);
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@ -147,6 +249,31 @@ Preinstruction Predecoder::decode8(uint16_t instruction) {
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return Preinstruction();
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}
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Preinstruction Predecoder::decodeB(uint16_t instruction) {
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// 4-100 (p204)
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switch(instruction & 0x0c0) {
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case 0x000: return decode<Operation::EORb>(instruction);
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case 0x040: return decode<Operation::EORw>(instruction);
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case 0x080: return decode<Operation::EORl>(instruction);
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default: break;
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}
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// 4-75 (p179)
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switch(instruction & 0x1c0) {
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case 0x000: return decode<Operation::CMPb>(instruction);
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case 0x040: return decode<Operation::CMPw>(instruction);
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case 0x080: return decode<Operation::CMPl>(instruction);
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// 4-77 (p181)
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case 0x0c0: return decode<Operation::CMPAw>(instruction);
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case 0x1c0: return decode<Operation::CMPAl>(instruction);
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default: break;
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}
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return Preinstruction();
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}
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Preinstruction Predecoder::decodeC(uint16_t instruction) {
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// 4-3 (p107)
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if((instruction & 0x1f0) == 0x100) return decode<Operation::ABCD>(instruction);
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@ -171,6 +298,7 @@ Preinstruction Predecoder::decodeC(uint16_t instruction) {
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case 0x148:
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case 0x188: return decode<Operation::EXG>(instruction);
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}
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return Preinstruction();
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}
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@ -179,7 +307,9 @@ Preinstruction Predecoder::decodeC(uint16_t instruction) {
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Preinstruction Predecoder::decode(uint16_t instruction) {
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// Divide first based on line.
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switch(instruction & 0xf000) {
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case 0x4000: return decode4(instruction);
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case 0x8000: return decode8(instruction);
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case 0xb000: return decodeB(instruction);
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case 0xc000: return decodeC(instruction);
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default: break;
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@ -26,7 +26,9 @@ class Predecoder {
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private:
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// Page by page decoders; each gets a bit ad hoc so
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// it is neater to separate them.
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Preinstruction decode4(uint16_t instruction);
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Preinstruction decode8(uint16_t instruction);
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Preinstruction decodeB(uint16_t instruction);
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Preinstruction decodeC(uint16_t instruction);
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// Specific instruction decoders.
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@ -17,6 +17,8 @@ namespace M68k {
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enum class Operation: uint8_t {
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Undefined,
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NOP,
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ABCD, SBCD, NBCD,
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ADDb, ADDw, ADDl,
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@ -37,6 +39,7 @@ enum class Operation: uint8_t {
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MOVEtoSR, MOVEfromSR,
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MOVEtoCCR,
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MOVEtoUSP, MOVEfromUSP,
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ORItoSR, ORItoCCR,
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ANDItoSR, ANDItoCCR,
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@ -45,10 +48,10 @@ enum class Operation: uint8_t {
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BTSTb, BTSTl,
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BCLRl, BCLRb,
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CMPb, CMPw, CMPl,
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CMPAw,
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CMPAw, CMPAl,
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TSTb, TSTw, TSTl,
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JMP, RTS,
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JMP, JSR, RTS,
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BRA, Bcc,
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DBcc,
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Scc,
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@ -80,7 +83,7 @@ enum class Operation: uint8_t {
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MULU, MULS,
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DIVU, DIVS,
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RTE_RTR,
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RTE, RTR,
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TRAP, TRAPV,
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CHK,
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@ -96,7 +99,7 @@ enum class Operation: uint8_t {
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LINK, UNLINK,
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STOP,
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STOP, RESET,
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};
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/// Indicates the addressing mode applicable to an operand.
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