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Ensures NMI and RST reset D on 65C02s.

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This commit is contained in:
Thomas Harte 2018-08-14 19:49:14 -04:00
parent 1eca4463b3
commit ddf45a0010
5 changed files with 24 additions and 10 deletions
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2
OSBindings/Mac/Clock SignalTests/Bridges/TestMachine6502.mm
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@ -40,7 +40,7 @@ static CPU::MOS6502::Register registerForRegister(CSTestMachine6502Register reg)
if(self) {
_processor = CPU::MOS6502::AllRAMProcessor::Processor(
is65C02 ? CPU::MOS6502::Personality::P65C02 : CPU::MOS6502::Personality::P6502);
is65C02 ? CPU::MOS6502::Personality::PWDC65C02 : CPU::MOS6502::Personality::P6502);
}
return self;

19
Processors/6502/AllRAM/6502AllRAM.cpp
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@ -15,10 +15,10 @@ using namespace CPU::MOS6502;
namespace {
class ConcreteAllRAMProcessor: public AllRAMProcessor, public BusHandler {
template <Personality personality> class ConcreteAllRAMProcessor: public AllRAMProcessor, public BusHandler {
public:
ConcreteAllRAMProcessor(Personality personality) :
mos6502_(personality, *this) {
ConcreteAllRAMProcessor() :
mos6502_(*this) {
mos6502_.set_power_on(false);
}
@ -63,11 +63,20 @@ class ConcreteAllRAMProcessor: public AllRAMProcessor, public BusHandler {
}
private:
CPU::MOS6502::Processor<ConcreteAllRAMProcessor, false> mos6502_;
CPU::MOS6502::Processor<personality, ConcreteAllRAMProcessor, false> mos6502_;
};
}
AllRAMProcessor *AllRAMProcessor::Processor(Personality personality) {
return new ConcreteAllRAMProcessor(personality);
#define Bind(p) case p: return new ConcreteAllRAMProcessor<p>();
switch(personality) {
default:
Bind(Personality::P6502)
Bind(Personality::PNES6502)
Bind(Personality::PSynertek65C02)
Bind(Personality::PWDC65C02)
Bind(Personality::PRockwell65C02)
}
#undef Bind
}

9
Processors/6502/Implementation/6502Implementation.hpp
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@ -152,10 +152,13 @@ if(number_of_cycles <= Cycles(0)) break;
case OperationRSTPickVector: nextAddress.full = 0xfffc; continue;
case CycleReadVectorLow: read_mem(pc_.bytes.low, nextAddress.full); break;
case CycleReadVectorHigh: read_mem(pc_.bytes.high, nextAddress.full+1); break;
case OperationSetI:
case OperationSetIRQFlags:
inverse_interrupt_flag_ = 0;
if(is_65c02(personality)) decimal_flag_ = false;
continue;
case OperationSetNMIRSTFlags:
if(is_65c02(personality)) decimal_flag_ = false;
continue;
case CyclePullPCL: s_++; read_mem(pc_.bytes.low, s_ | 0x100); break;
case CyclePullPCH: s_++; read_mem(pc_.bytes.high, s_ | 0x100); break;
@ -681,6 +684,7 @@ inline const ProcessorStorage::MicroOp *ProcessorStorage::get_reset_program() {
CycleNoWritePush,
OperationRSTPickVector,
CycleNoWritePush,
OperationSetNMIRSTFlags,
CycleReadVectorLow,
CycleReadVectorHigh,
OperationMoveToNextProgram
@ -697,7 +701,7 @@ inline const ProcessorStorage::MicroOp *ProcessorStorage::get_irq_program() {
OperationBRKPickVector,
OperationSetOperandFromFlags,
CyclePushOperand,
OperationSetI,
OperationSetIRQFlags,
CycleReadVectorLow,
CycleReadVectorHigh,
OperationMoveToNextProgram
@ -714,6 +718,7 @@ inline const ProcessorStorage::MicroOp *ProcessorStorage::get_nmi_program() {
OperationNMIPickVector,
OperationSetOperandFromFlags,
CyclePushOperand,
OperationSetNMIRSTFlags,
CycleReadVectorLow,
CycleReadVectorHigh,
OperationMoveToNextProgram

2
Processors/6502/Implementation/6502Storage.cpp
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@ -80,7 +80,7 @@ ProcessorStorage::ProcessorStorage(Personality personality) {
overflow_flag_ &= Flag::Overflow;
const InstructionList operations_6502[256] = {
/* 0x00 BRK */ Program(CycleIncPCPushPCH, CyclePushPCL, OperationBRKPickVector, OperationSetOperandFromFlagsWithBRKSet, CyclePushOperand, OperationSetI, CycleReadVectorLow, CycleReadVectorHigh),
/* 0x00 BRK */ Program(CycleIncPCPushPCH, CyclePushPCL, OperationBRKPickVector, OperationSetOperandFromFlagsWithBRKSet, CyclePushOperand, OperationSetIRQFlags, CycleReadVectorLow, CycleReadVectorHigh),
/* 0x01 ORA x, ind */ IndexedIndirectRead(OperationORA),
/* 0x02 JAM */ JAM, /* 0x03 ASO x, ind */ IndexedIndirectReadModifyWrite(OperationASO),
/* 0x04 NOP zpg */ ZeroNop(), /* 0x05 ORA zpg */ ZeroRead(OperationORA),

2
Processors/6502/Implementation/6502Storage.hpp
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@ -25,7 +25,7 @@ class ProcessorStorage {
enum MicroOp {
CycleFetchOperation, CycleFetchOperand, OperationDecodeOperation, CycleIncPCPushPCH,
CyclePushPCH, CyclePushPCL, CyclePushA, CyclePushOperand,
CyclePushX, CyclePushY, OperationSetI,
CyclePushX, CyclePushY, OperationSetIRQFlags, OperationSetNMIRSTFlags,
OperationBRKPickVector, OperationNMIPickVector, OperationRSTPickVector,
CycleReadVectorLow, CycleReadVectorHigh,