From de7d9ba471eb4d9c1879d426fa8e6b0e1b509bae Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Sun, 3 Apr 2022 08:06:59 -0400 Subject: [PATCH] Add further floating point tests. --- InstructionSets/PowerPC/Instruction.hpp | 47 +++++++++++++++++-- .../DingusdevPowerPCTests.mm | 40 +++++++++++++++- 2 files changed, 81 insertions(+), 6 deletions(-) diff --git a/InstructionSets/PowerPC/Instruction.hpp b/InstructionSets/PowerPC/Instruction.hpp index b5a58979c..5e654450d 100644 --- a/InstructionSets/PowerPC/Instruction.hpp +++ b/InstructionSets/PowerPC/Instruction.hpp @@ -102,7 +102,15 @@ enum class Operation: uint8_t { /// rD(), rA(), rB() lscbxx, - maskgx, maskirx, + /// Mask generate. + /// maskg maskg. + /// rA(), rS(), rB() [rc()] + maskgx, + + /// Mask insert from register. + /// maskir maskir. + /// rA(), rS(), rB() [rc()] + maskirx, /// Multiply. /// mul mul. mulo mulo. @@ -332,7 +340,7 @@ enum class Operation: uint8_t { /// Floating point absolute. /// fabs fabs. - /// frD(), frA(), frB() [rc()] + /// frD(), frB() [rc()] fabsx, /// Floating point add. @@ -385,6 +393,9 @@ enum class Operation: uint8_t { /// frD(), frA(), frC(), frB() [rc()] fmaddsx, + /// Floating point register move. + /// fmr fmr. + /// frD(), frB() [rc()] fmrx, /// Floating point multiply subtract. @@ -407,7 +418,15 @@ enum class Operation: uint8_t { /// frD(), frA(), frC() [rc()] fmulsx, - fnabsx, fnegx, + /// Floating negative absolute value. + /// fnabs fnabs. + /// frD(), frB() [rc()] + fnabsx, + + /// Floating negative. + /// fneg fneg. + /// frD(), frB() [rc()] + fnegx, /// Floating point negative multiply add. /// fnmadd fnmadd. @@ -429,8 +448,12 @@ enum class Operation: uint8_t { /// frD(), frA(), frC(), frB() [rc()] fnmsubsx, - frspx, fsubx, fsubsx, + /// Floating point round to single precision. + /// frsp frsp. + /// frD(), frB() [rc()] + frspx, + fsubx, fsubsx, icbi, isync, /// Load byte and zero. @@ -581,7 +604,18 @@ enum class Operation: uint8_t { /// lwzx lwzx, - mcrf, mcrfs, mcrxr, + /// Move condition register field. + /// mcrf + /// crfD(), crfS() + mcrf, + + /// Move to condition register from FPSCR. + /// mcrfs + /// crfD(), crfS() + mcrfs, + + + mcrxr, mfcr, mffsx, mfmsr, mfspr, mfsr, mfsrin, /// Move to condition register fields. @@ -837,6 +871,9 @@ enum class Operation: uint8_t { /// frD(), frB() [rc()] fresx, + /// Floating point reciprocal square root estimation. + /// frsqrte frsqrte. + /// frD(), frB() [rc()] frsqrtex, /// Floating point select. diff --git a/OSBindings/Mac/Clock SignalTests/DingusdevPowerPCTests.mm b/OSBindings/Mac/Clock SignalTests/DingusdevPowerPCTests.mm index f873206f3..fc9842ba3 100644 --- a/OSBindings/Mac/Clock SignalTests/DingusdevPowerPCTests.mm +++ b/OSBindings/Mac/Clock SignalTests/DingusdevPowerPCTests.mm @@ -98,6 +98,11 @@ NSString *condition(uint32_t code) { } } +NSString *conditionreg(uint32_t code) { + return [NSString stringWithFormat:@"cr%d", code]; +} + + NSString *offset(Instruction instruction) { NSString *const hexPart = [NSString stringWithFormat:@"%s%X", (instruction.d() < 0) ? "-0x" : "0x", abs(instruction.d())]; @@ -519,7 +524,6 @@ NSString *offset(Instruction instruction) { AssertEqualFR(columns[5], instruction.frB()); \ break; - fDfAfB(fabsx); fDfAfB(faddx); fDfAfB(faddsx); fDfAfB(fsubx); @@ -529,6 +533,28 @@ NSString *offset(Instruction instruction) { #undef fDfAfB +#define fDfB(x) \ + case Operation::x: \ + AssertEqualOperationNameE(operation, @#x, instruction); \ + AssertEqualFR(columns[3], instruction.frD()); \ + AssertEqualFR(columns[4], instruction.frB()); \ + break; + + fDfB(fabsx); + fDfB(fnabsx); + fDfB(fnegx); + fDfB(frsqrtex); + fDfB(frspx); + fDfB(fctiwx); + fDfB(fctiwzx); + fDfB(fctidx); + fDfB(fctidzx); + fDfB(fcfidx); + fDfB(fresx); + fDfB(fmrx); + +#undef fDfB + #define fDfAfC(x) \ case Operation::x: \ AssertEqualOperationNameE(operation, @#x, instruction); \ @@ -627,6 +653,18 @@ NSString *offset(Instruction instruction) { #undef fSDA +#define crfDS(x) \ + case Operation::x: \ + AssertEqualOperationName(operation, @#x, instruction); \ + XCTAssertEqualObjects(columns[3], conditionreg(instruction.crfD())); \ + XCTAssertEqualObjects(columns[4], conditionreg(instruction.crfS())); \ + break; + + crfDS(mcrf); + crfDS(mcrfs); + +#undef crfDS + case Operation::bcx: case Operation::bclrx: case Operation::bcctrx: {