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https://github.com/TomHarte/CLK.git
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Removes unused state and implements AND output readback.
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@ -225,14 +225,10 @@ uint8_t AY38910::get_register_value() {
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};
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if(selected_register_ > 15) return 0xff;
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switch(selected_register_) {
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default: return registers_[selected_register_] & register_masks[selected_register_];
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case 14: return (registers_[0x7] & 0x40) ? registers_[14] : port_inputs_[0];
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case 15: return (registers_[0x7] & 0x80) ? registers_[15] : port_inputs_[1];
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}
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return registers_[selected_register_] & register_masks[selected_register_];
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}
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// MARK: - Port handling
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// MARK: - Port querying
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uint8_t AY38910::get_port_output(bool port_b) {
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return registers_[port_b ? 15 : 14];
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@ -250,11 +246,16 @@ void AY38910::set_data_input(uint8_t r) {
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}
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uint8_t AY38910::get_data_output() {
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if(control_state_ == Read && selected_register_ >= 14) {
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if(port_handler_) {
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return port_handler_->get_port_input(selected_register_ == 15);
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} else {
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return 0xff;
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if(control_state_ == Read && selected_register_ >= 14 && selected_register_ < 16) {
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// Per http://cpctech.cpc-live.com/docs/psgnotes.htm if a port is defined as output then the
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// value returned to the CPU when reading it is the and of the output value and any input.
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// If it's defined as input then you just get the input.
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const uint8_t mask = port_handler_ ? port_handler_->get_port_input(selected_register_ == 15) : 0xff;
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switch(selected_register_) {
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default: break;
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case 14: return mask & ((registers_[0x7] & 0x40) ? registers_[14] : 0xff);
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case 15: return mask & ((registers_[0x7] & 0x80) ? registers_[15] : 0xff);
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}
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}
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return data_output_;
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@ -276,6 +277,7 @@ void AY38910::set_control_lines(ControlLines control_lines) {
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}
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void AY38910::update_bus() {
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// Assume no output, unless this turns out to be a read.
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data_output_ = 0xff;
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switch(control_state_) {
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default: break;
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@ -94,7 +94,6 @@ class AY38910: public ::Outputs::Speaker::SampleSource {
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int selected_register_ = 0;
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uint8_t registers_[16] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
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uint8_t output_registers_[16] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
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uint8_t port_inputs_[2];
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int master_divider_ = 0;
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