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Makes assumption that the address bus just holds its value during an internal operation.

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This commit is contained in:
Thomas Harte 2021-04-10 12:00:53 -04:00
parent b09c5538c6
commit e0736435f8
4 changed files with 21 additions and 15 deletions
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28
OSBindings/Mac/Clock SignalTests/Z80ContentionTests.mm
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@ -388,13 +388,13 @@ struct ContentionCheck {
[self validate48Contention:{ [self validate48Contention:{
{initial_pc, 4}, {initial_pc, 4},
{initial_ir+1, 1}, {initial_ir, 1},
{initial_ir+1, 1}, {initial_ir, 1},
{initial_ir+1, 1}, {initial_ir, 1},
{initial_ir+1, 1}, {initial_ir, 1},
{initial_ir+1, 1}, {initial_ir, 1},
{initial_ir+1, 1}, {initial_ir, 1},
{initial_ir+1, 1}, {initial_ir, 1},
} z80:z80]; } z80:z80];
[self validatePlus3Contention:{{initial_pc, 11}} z80:z80]; [self validatePlus3Contention:{{initial_pc, 11}} z80:z80];
} }
@ -414,13 +414,13 @@ struct ContentionCheck {
[self validate48Contention:{ [self validate48Contention:{
{initial_pc, 4}, {initial_pc, 4},
{initial_pc+1, 4}, {initial_pc+1, 4},
{initial_ir+2, 1}, {initial_ir+1, 1},
{initial_ir+2, 1}, {initial_ir+1, 1},
{initial_ir+2, 1}, {initial_ir+1, 1},
{initial_ir+2, 1}, {initial_ir+1, 1},
{initial_ir+2, 1}, {initial_ir+1, 1},
{initial_ir+2, 1}, {initial_ir+1, 1},
{initial_ir+2, 1}, {initial_ir+1, 1},
} z80:z80]; } z80:z80];
[self validatePlus3Contention:{{initial_pc, 4}, {initial_pc+1, 11}} z80:z80]; [self validatePlus3Contention:{{initial_pc, 4}, {initial_pc+1, 11}} z80:z80];
} }

4
Processors/Z80/Implementation/Z80Implementation.hpp
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@ -82,6 +82,10 @@ template < class T,
} }
number_of_cycles_ -= operation->machine_cycle.length; number_of_cycles_ -= operation->machine_cycle.length;
last_request_status_ = request_status_; last_request_status_ = request_status_;
// TODO: eliminate this conditional if all bus cycles have an address filled in.
last_address_bus_ = operation->machine_cycle.address ? *operation->machine_cycle.address : 0xdead;
number_of_cycles_ -= bus_handler_.perform_machine_cycle(operation->machine_cycle); number_of_cycles_ -= bus_handler_.perform_machine_cycle(operation->machine_cycle);
if(uses_bus_request && bus_request_line_) goto do_bus_acknowledge; if(uses_bus_request && bus_request_line_) goto do_bus_acknowledge;
break; break;

2
Processors/Z80/Implementation/Z80Storage.cpp
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@ -62,7 +62,7 @@ ProcessorStorage::ProcessorStorage() {
#define Input(addr, val) BusOp(InputStart(addr, val)), BusOp(InputWait(addr, val, false)), BusOp(InputWait(addr, val, true)), BusOp(InputEnd(addr, val)) #define Input(addr, val) BusOp(InputStart(addr, val)), BusOp(InputWait(addr, val, false)), BusOp(InputWait(addr, val, true)), BusOp(InputEnd(addr, val))
#define Output(addr, val) BusOp(OutputStart(addr, val)), BusOp(OutputWait(addr, val, false)), BusOp(OutputWait(addr, val, true)), BusOp(OutputEnd(addr, val)) #define Output(addr, val) BusOp(OutputStart(addr, val)), BusOp(OutputWait(addr, val, false)), BusOp(OutputWait(addr, val, true)), BusOp(OutputEnd(addr, val))
#define InternalOperation(len) {MicroOp::BusOperation, nullptr, nullptr, {PartialMachineCycle::Internal, HalfCycles(len), &ir_.full, nullptr, false}} #define InternalOperation(len) {MicroOp::BusOperation, nullptr, nullptr, {PartialMachineCycle::Internal, HalfCycles(len), &last_address_bus_, nullptr, false}}
/// A sequence is a series of micro-ops that ends in a move-to-next-program operation. /// A sequence is a series of micro-ops that ends in a move-to-next-program operation.
#define Sequence(...) { __VA_ARGS__, {MicroOp::MoveToNextProgram} } #define Sequence(...) { __VA_ARGS__, {MicroOp::MoveToNextProgram} }

2
Processors/Z80/Implementation/Z80Storage.hpp
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@ -149,6 +149,8 @@ class ProcessorStorage {
// that knowledge of what the last opcode did is necessary to get bits 5 & 3 // that knowledge of what the last opcode did is necessary to get bits 5 & 3
// correct for SCF and CCF. // correct for SCF and CCF.
uint16_t last_address_bus_ = 0; // The value most recently put out on the address bus.
HalfCycles number_of_cycles_; HalfCycles number_of_cycles_;
enum Interrupt: uint8_t { enum Interrupt: uint8_t {