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Further mildly increases logging.
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parent
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commit
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@ -95,6 +95,7 @@ class ConcreteMachine:
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// directly to the chip enables.
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// directly to the chip enables.
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if((address & 0xe0'0000) == 0xa0'0000) {
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if((address & 0xe0'0000) == 0xa0'0000) {
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const int reg = address >> 8;
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const int reg = address >> 8;
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LOG("CIA access: " << PADHEX(4) << *cycle.address);
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if(cycle.operation & Microcycle::Read) {
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if(cycle.operation & Microcycle::Read) {
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uint16_t result = 0xffff;
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uint16_t result = 0xffff;
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@ -203,6 +204,7 @@ class ConcreteMachine:
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} else {
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} else {
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// This'll do for open bus, for now.
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// This'll do for open bus, for now.
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cycle.set_value16(0xffff);
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cycle.set_value16(0xffff);
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LOG("Unmapped access to " << PADHEX(4) << *cycle.address);
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}
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}
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}
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}
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} else {
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} else {
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