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Takes a second pass at DIVS timing, seeming to correct that side of things.
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@ -1049,22 +1049,28 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
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break;
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break;
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}
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}
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int32_t dividend = int32_t(destination()->full);
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const int32_t signed_dividend = int32_t(destination()->full);
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int32_t divisor = s_extend16(source()->halves.low.full);
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const int32_t signed_divisor = s_extend16(source()->halves.low.full);
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const int64_t quotient = int64_t(dividend) / int64_t(divisor);
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const auto result_sign =
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( (0 <= signed_dividend) - (signed_dividend < 0) ) *
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( (0 <= signed_divisor) - (signed_divisor < 0) );
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const uint32_t dividend = uint32_t(abs(signed_dividend));
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const uint32_t divisor = uint32_t(abs(signed_divisor));
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int cycles_expended = 12; // Covers the nn nnn n to get beyond the sign test.
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int cycles_expended = 12; // Covers the nn nnn n to get beyond the sign test.
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if(dividend < 0) {
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if(signed_dividend < 0) {
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cycles_expended += 2; // An additional microycle applies if the dividend is negative.
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cycles_expended += 2; // An additional microycle applies if the dividend is negative.
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}
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}
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// Check for overflow. If it exists, work here is already done.
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// Check for overflow. If it exists, work here is already done.
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if(quotient > 32767 || quotient < -32768) {
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const auto quotient = dividend / divisor;
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if(quotient > 32767) {
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overflow_flag_ = 1;
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overflow_flag_ = 1;
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set_next_microcycle_length(HalfCycles(3*2*2));
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set_next_microcycle_length(HalfCycles(6*2*2));
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// These are officially undefined for results that overflow, so the below is a guess.
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// These are officially undefined for results that overflow, so the below is a guess.
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zero_result_ = decltype(zero_result_)(divisor & 0xffff);
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zero_result_ = decltype(zero_result_)(dividend);
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negative_flag_ = zero_result_ & 0x8000;
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negative_flag_ = zero_result_ & 0x8000;
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break;
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break;
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@ -1074,26 +1080,25 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
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negative_flag_ = zero_result_ & 0x8000;
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negative_flag_ = zero_result_ & 0x8000;
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overflow_flag_ = 0;
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overflow_flag_ = 0;
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// TODO: check sign rules here; am I necessarily giving the remainder the correct sign?
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const uint16_t remainder = uint16_t(signed_dividend % signed_divisor);
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// (and, if not, am I counting it in the correct direction?)
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const int signed_quotient = result_sign*int(quotient);
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const uint16_t remainder = uint16_t(dividend % divisor);
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destination()->halves.high.full = remainder;
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destination()->halves.high.full = remainder;
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destination()->halves.low.full = uint16_t(quotient);
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destination()->halves.low.full = uint16_t(signed_quotient);
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// Algorithm here: there is a fixed three-microcycle cost per bit set
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// Algorithm here: there is a fixed cost per unset bit
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// in the unsigned quotient; there is an additional microcycle for
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// in the first 15 bits of the unsigned quotient.
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// every bit that is set. Also, since the possibility of overflow
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auto positive_quotient_bits = ~quotient & 0xfffe;
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// was already dealt with, it's now a smaller number.
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int positive_quotient_bits = int(abs(quotient)) & 0xfffe;
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convert_to_bit_count_16(positive_quotient_bits);
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convert_to_bit_count_16(positive_quotient_bits);
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cycles_expended += 2 * positive_quotient_bits;
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cycles_expended += 2 * positive_quotient_bits;
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// There's then no way to terminate the loop that isn't at least six cycles long.
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// There's then no way to terminate the loop that isn't at least ten cycles long;
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cycles_expended += 6;
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// there's also a fixed overhead per bit. The two together add up to the 104 below.
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cycles_expended += 104;
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if(divisor < 0) {
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// This picks up at 'No more bits' in yacht.txt's diagram.
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if(signed_divisor < 0) {
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cycles_expended += 2;
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cycles_expended += 2;
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} else if(dividend < 0) {
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} else if(signed_dividend < 0) {
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cycles_expended += 4;
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cycles_expended += 4;
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}
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}
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set_next_microcycle_length(HalfCycles(cycles_expended * 2));
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set_next_microcycle_length(HalfCycles(cycles_expended * 2));
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