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Corrects immediate instruction length, muddles through to having to parse a second program segment.

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Albeit with JSR not yet properly implemented.
This commit is contained in:
Thomas Harte 2021-01-19 22:12:18 -05:00
parent b0c790f3c6
commit e502d76371
4 changed files with 35 additions and 9 deletions
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2
InstructionSets/M50740/Decoder.cpp
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@ -144,7 +144,7 @@ Instruction Decoder::instrucion_for_opcode(uint8_t opcode) {
Map(0x96, STX, ZeroPageX); Map(0x97, BBC4, ZeroPageRelative);
Map(0x98, TYA, Implied); Map(0x99, STA, AbsoluteY);
Map(0x9a, TXS, AbsoluteY); Map(0x9b, CLB4, Accumulator);
Map(0x9a, TXS, Implied); Map(0x9b, CLB4, Accumulator);
Map(0x9d, ADC, AbsoluteX);
Map(0x9f, CLB4, ZeroPage);

30
InstructionSets/M50740/Executor.cpp
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@ -42,7 +42,7 @@ void Executor::set_rom(const std::vector<uint8_t> &rom) {
void Executor::reset() {
// Just jump to the reset vector.
set_program_counter(uint16_t(memory_[0x1ffe] | (memory_[0x1fff] << 8)) & 0x1fff);
set_program_counter(uint16_t(memory_[0x1ffe] | (memory_[0x1fff] << 8)));
}
template <Operation operation, AddressingMode addressing_mode> void Executor::perform() {
@ -55,6 +55,8 @@ template <Operation operation, AddressingMode addressing_mode> void Executor::pe
#define next8() memory_[(program_counter_ + 1) & 0x1fff]
#define next16() (memory_[(program_counter_ + 1) & 0x1fff] | (memory_[(program_counter_ + 2) & 0x1fff] << 8))
printf("%d %d\n", int(operation), int(addressing_mode));
// Underlying assumption below: the instruction stream will never
// overlap with IO ports.
switch(addressing_mode) {
@ -130,8 +132,25 @@ template <Operation operation, AddressingMode addressing_mode> void Executor::pe
#undef next16
#undef next8
program_counter_ += 1 + size(addressing_mode);
// Check for a branch; those don't go through the memory accesses below.
switch(operation) {
case Operation::JMP:
set_program_counter(uint16_t(address));
return;
case Operation::JSR:
// TODO: push!
set_program_counter(uint16_t(address));
return;
/* TODO: all other types of branches and calls. */
default: break;
}
assert(access_type(operation) != AccessType::None);
// TODO: full reading/writing logic here; only the first 96 bytes are RAM,
@ -159,6 +178,13 @@ template <Operation operation> void Executor::perform(uint8_t *operand [[maybe_u
case Operation::STX: *operand = x_; break;
case Operation::STY: *operand = y_; break;
case Operation::TXA: set_nz(a_ = x_); break;
case Operation::TYA: set_nz(a_ = y_); break;
case Operation::TXS: s_ = x_; break;
case Operation::TAX: set_nz(x_ = a_); break;
case Operation::TAY: set_nz(y_ = a_); break;
case Operation::TSX: set_nz(x_ = s_); break;
case Operation::SEB0: case Operation::SEB1: case Operation::SEB2: case Operation::SEB3:
case Operation::SEB4: case Operation::SEB5: case Operation::SEB6: case Operation::SEB7:
*operand |= 1 << (int(operation) - int(Operation::SEB0));

2
InstructionSets/M50740/Executor.hpp
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@ -46,7 +46,7 @@ class Executor: public CachingExecutor {
*/
inline void parse(uint16_t start, uint16_t closing_bound) {
Parser<Executor, false> parser;
parser.parse(*this, memory_, start, closing_bound);
parser.parse(*this, memory_, start & 0x1fff, closing_bound);
}
private:

10
InstructionSets/M50740/Instruction.hpp
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@ -16,10 +16,10 @@ namespace InstructionSet {
namespace M50740 {
enum class AddressingMode {
Implied, Accumulator, Immediate,
Absolute, AbsoluteX, AbsoluteY,
ZeroPage, ZeroPageX, ZeroPageY,
XIndirect, IndirectY,
Implied, Accumulator, Immediate,
Absolute, AbsoluteX, AbsoluteY,
ZeroPage, ZeroPageX, ZeroPageY,
XIndirect, IndirectY,
Relative,
AbsoluteIndirect, ZeroPageIndirect,
SpecialPage,
@ -33,7 +33,7 @@ static constexpr auto MinAddressingMode = int(AddressingMode::Implied);
constexpr int size(AddressingMode mode) {
// This is coupled to the AddressingMode list above; be careful!
constexpr int sizes[] = {
0, 0, 0,
0, 0, 1,
2, 2, 2,
1, 1, 1,
1, 1,