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Merge pull request #71 from TomHarte/IRQBenchTest
Introduces a one-cycle cost to setting 6522 timers
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commit
e5de9c8607
@ -90,7 +90,7 @@ template <class T> class MOS6522 {
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_registers.interrupt_flags &= ~InterruptFlag::Timer1;
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if(address == 0x05)
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{
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_registers.timer[0] = _registers.timer_latch[0];
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_registers.next_timer[0] = _registers.timer_latch[0];
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_timer_is_running[0] = true;
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}
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reevaluate_interrupts();
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@ -100,7 +100,7 @@ template <class T> class MOS6522 {
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case 0x8: _registers.timer_latch[1] = value; break;
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case 0x9:
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_registers.interrupt_flags &= ~InterruptFlag::Timer2;
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_registers.timer[1] = _registers.timer_latch[1] | (uint16_t)(value << 8);
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_registers.next_timer[1] = _registers.timer_latch[1] | (uint16_t)(value << 8);
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_timer_is_running[1] = true;
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reevaluate_interrupts();
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break;
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@ -242,7 +242,9 @@ template <class T> class MOS6522 {
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else\
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_registers.timer[0] --;\
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\
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_registers.timer[1] --;
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_registers.timer[1] --; \
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if(_registers.next_timer[0] >= 0) { _registers.timer[0] = (uint16_t)_registers.next_timer[0]; _registers.next_timer[0] = -1; }\
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if(_registers.next_timer[1] >= 0) { _registers.timer[1] = (uint16_t)_registers.next_timer[1]; _registers.next_timer[1] = -1; }\
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// IRQ is raised on the half cycle after overflow
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#define phase1() \
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@ -367,6 +369,7 @@ template <class T> class MOS6522 {
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struct Registers {
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uint8_t output[2], input[2], data_direction[2];
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uint16_t timer[2], timer_latch[2], last_timer[2];
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int next_timer[2];
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uint8_t shift;
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uint8_t auxiliary_control, peripheral_control;
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uint8_t interrupt_flags, interrupt_enable;
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@ -377,7 +380,8 @@ template <class T> class MOS6522 {
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output{0, 0}, input{0, 0}, data_direction{0, 0},
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auxiliary_control(0), peripheral_control(0),
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interrupt_flags(0), interrupt_enable(0),
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last_timer{0, 0}, timer_needs_reload(false) {}
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last_timer{0, 0}, timer_needs_reload(false),
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next_timer{-1, -1} {}
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} _registers;
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// control state
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@ -52,7 +52,7 @@ unsigned int Machine::perform_bus_operation(CPU6502::BusOperation operation, uin
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// 024D = 0 => fast; otherwise slow
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// E6C9 = read byte: return byte in A
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if(address == 0xe6c9 && _use_fast_tape_hack && operation == CPU6502::BusOperation::ReadOpcode)
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if(address == 0xe6c9 && _use_fast_tape_hack && operation == CPU6502::BusOperation::ReadOpcode && _via.tape->has_tape() && !_via.tape->get_tape()->is_at_end())
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{
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uint8_t next_byte = _via.tape->get_next_byte(!_ram[0x024d]);
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set_value_of_register(CPU6502::A, next_byte);
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@ -24,6 +24,9 @@ class MOS6522Tests: XCTestCase {
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$0.setValue(10, forRegister: 4)
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$0.setValue(0, forRegister: 5)
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// complete the setting cycle
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$0.run(forHalfCycles: 2)
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// run for 5 cycles
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$0.run(forHalfCycles: 10)
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@ -42,6 +45,9 @@ class MOS6522Tests: XCTestCase {
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// change the low-byte latch
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$0.setValue(0x40, forRegister: 8)
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// complete the cycle
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$0.run(forHalfCycles: 2)
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// chek that the new latched value hasn't been copied
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XCTAssert($0.value(forRegister: 8) == 0x10, "Low order byte should be 0x10; was \($0.value(forRegister: 8))")
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XCTAssert($0.value(forRegister: 9) == 0x20, "High order byte should be 0x20; was \($0.value(forRegister: 9))")
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@ -49,6 +55,9 @@ class MOS6522Tests: XCTestCase {
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// write the low-byte latch
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$0.setValue(0x50, forRegister: 9)
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// complete the cycle
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$0.run(forHalfCycles: 2)
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// chek that the latched value has been copied
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XCTAssert($0.value(forRegister: 8) == 0x40, "Low order byte should be 0x50; was \($0.value(forRegister: 8))")
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XCTAssert($0.value(forRegister: 9) == 0x50, "High order byte should be 0x40; was \($0.value(forRegister: 9))")
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@ -63,6 +72,9 @@ class MOS6522Tests: XCTestCase {
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$0.setValue(0x40, forRegister: 11)
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$0.setValue(0x40 | 0x80, forRegister: 14)
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// complete the cycle to set initial values
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$0.run(forHalfCycles: 2)
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// run for 16 cycles
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$0.run(forHalfCycles: 32)
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@ -103,6 +115,9 @@ class MOS6522Tests: XCTestCase {
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// ask to output 0x8c
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$0.setValue(0x8c, forRegister: 0)
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// complete the cycle
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$0.run(forHalfCycles: 2)
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// set current input as 0xda
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$0.portBInput = 0xda
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@ -90,11 +90,12 @@ class Speaker {
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protected:
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void enqueue(std::function<void(void)> function)
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{
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_queue->enqueue(function);
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function();
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// _queue->enqueue(function);
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}
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void flush()
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{
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_queue->flush();
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// _queue->flush();
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}
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std::unique_ptr<int16_t> _buffer_in_progress;
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