mirror of
https://github.com/TomHarte/CLK.git
synced 2025-01-11 08:30:55 +00:00
Corrected typo: the input to an AY is BDIR, not BCDIR.
This commit is contained in:
parent
3b292273c7
commit
e6854ff8db
@ -244,12 +244,12 @@ void AY38910::set_control_lines(ControlLines control_lines) {
|
|||||||
switch((int)control_lines) {
|
switch((int)control_lines) {
|
||||||
default: new_state = Inactive; break;
|
default: new_state = Inactive; break;
|
||||||
|
|
||||||
case (int)(BCDIR | BC2 | BC1):
|
case (int)(BDIR | BC2 | BC1):
|
||||||
case BCDIR:
|
case BDIR:
|
||||||
case BC1: new_state = LatchAddress; break;
|
case BC1: new_state = LatchAddress; break;
|
||||||
|
|
||||||
case (int)(BC2 | BC1): new_state = Read; break;
|
case (int)(BC2 | BC1): new_state = Read; break;
|
||||||
case (int)(BCDIR | BC2): new_state = Write; break;
|
case (int)(BDIR | BC2): new_state = Write; break;
|
||||||
}
|
}
|
||||||
|
|
||||||
if(new_state != control_state_) {
|
if(new_state != control_state_) {
|
||||||
|
@ -29,7 +29,7 @@ class AY38910: public ::Outputs::Filter<AY38910> {
|
|||||||
enum ControlLines {
|
enum ControlLines {
|
||||||
BC1 = (1 << 0),
|
BC1 = (1 << 0),
|
||||||
BC2 = (1 << 1),
|
BC2 = (1 << 1),
|
||||||
BCDIR = (1 << 2)
|
BDIR = (1 << 2)
|
||||||
};
|
};
|
||||||
|
|
||||||
/// Sets the value the AY would read from its data lines if it were not outputting.
|
/// Sets the value the AY would read from its data lines if it were not outputting.
|
||||||
|
@ -263,7 +263,7 @@ class i8255PortHandler : public Intel::i8255::PortHandler {
|
|||||||
// TODO: set casette output: ((value >> 5) & 1)
|
// TODO: set casette output: ((value >> 5) & 1)
|
||||||
ay_->set_control_lines(
|
ay_->set_control_lines(
|
||||||
(GI::AY38910::ControlLines)(
|
(GI::AY38910::ControlLines)(
|
||||||
((value & 0x80) ? GI::AY38910::BCDIR : 0) |
|
((value & 0x80) ? GI::AY38910::BDIR : 0) |
|
||||||
((value & 0x40) ? GI::AY38910::BC1 : 0) |
|
((value & 0x40) ? GI::AY38910::BC1 : 0) |
|
||||||
GI::AY38910::BC2
|
GI::AY38910::BC2
|
||||||
));
|
));
|
||||||
|
@ -244,7 +244,7 @@ void Machine::VIA::run_for(const Cycles cycles) {
|
|||||||
|
|
||||||
void Machine::VIA::update_ay() {
|
void Machine::VIA::update_ay() {
|
||||||
ay8910->run_for(cycles_since_ay_update_.flush());
|
ay8910->run_for(cycles_since_ay_update_.flush());
|
||||||
ay8910->set_control_lines( (GI::AY38910::ControlLines)((ay_bdir_ ? GI::AY38910::BCDIR : 0) | (ay_bc1_ ? GI::AY38910::BC1 : 0) | GI::AY38910::BC2));
|
ay8910->set_control_lines( (GI::AY38910::ControlLines)((ay_bdir_ ? GI::AY38910::BDIR : 0) | (ay_bc1_ ? GI::AY38910::BC1 : 0) | GI::AY38910::BC2));
|
||||||
}
|
}
|
||||||
|
|
||||||
#pragma mark - TapePlayer
|
#pragma mark - TapePlayer
|
||||||
|
Loading…
x
Reference in New Issue
Block a user