From 3e09afbb59bff64910b8fbcb83ef5e54d5604d94 Mon Sep 17 00:00:00 2001
From: Thomas Harte <TomHarte@users.noreply.github.com>
Date: Wed, 21 Jun 2023 11:57:09 -0400
Subject: [PATCH 01/14] Remove errant square bracket.
---
InstructionSets/x86/Instruction.hpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/InstructionSets/x86/Instruction.hpp b/InstructionSets/x86/Instruction.hpp
index 9fc8a8c54..2c6e7bd8a 100644
--- a/InstructionSets/x86/Instruction.hpp
+++ b/InstructionSets/x86/Instruction.hpp
@@ -224,7 +224,7 @@ enum class Operation: uint8_t {
/// current EFLAGS DF flag.
INS,
/// Outputs a byte, word or double word from ES:[e]DI to the port specified by DX,
- /// incrementing or decrementing [e]DI as per the current EFLAGS DF flag.]
+ /// incrementing or decrementing [e]DI as per the current EFLAGS DF flag.
OUTS,
/// Pushes all general purpose registers to the stack, in the order:
From e9347168e61c071e04edfb397d050652ce0780cf Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Fri, 28 Jul 2023 10:53:02 -0400
Subject: [PATCH 02/14] Don't alter the data bank upon BRK, COP, IRQ, etc.
---
Processors/65816/Implementation/65816Implementation.hpp | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Processors/65816/Implementation/65816Implementation.hpp b/Processors/65816/Implementation/65816Implementation.hpp
index bbb9dcedc..230d3723a 100644
--- a/Processors/65816/Implementation/65816Implementation.hpp
+++ b/Processors/65816/Implementation/65816Implementation.hpp
@@ -441,7 +441,9 @@ template <typename BusHandler, bool uses_ready_line> void Processor<BusHandler,
if(registers_.emulation_flag) {
if(exception_is_interrupt_) data_buffer_.value &= ~uint32_t(Flag::Break);
data_buffer_.size = 3;
- registers_.data_bank = 0;
+ if(pending_exceptions_ & (Reset | PowerOn)) {
+ registers_.data_bank = 0;
+ }
++next_op_;
} else {
data_buffer_.value |= registers_.program_bank << 8; // The PBR is always held such that
From 0f1468adfd8581421f058ef847259a23a3daa7ab Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Fri, 28 Jul 2023 13:39:21 -0400
Subject: [PATCH 03/14] Correct wrapping behaviour for (d, x).
---
.../Implementation/65816Implementation.hpp | 17 +++++++++++------
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/Processors/65816/Implementation/65816Implementation.hpp b/Processors/65816/Implementation/65816Implementation.hpp
index 230d3723a..c11705c1b 100644
--- a/Processors/65816/Implementation/65816Implementation.hpp
+++ b/Processors/65816/Implementation/65816Implementation.hpp
@@ -359,15 +359,20 @@ template <typename BusHandler, bool uses_ready_line> void Processor<BusHandler,
continue;
case OperationConstructDirectIndexedIndirect:
- data_address_ = (
- ((registers_.direct + registers_.x.full + instruction_buffer_.value) & registers_.e_masks[1]) +
- (registers_.direct & registers_.e_masks[0])
- ) & 0xffff;
- data_address_increment_mask_ = 0x00'ff'ff;
-
+ // Emulation mode plus DL = 0 is required for 6502-style functionality where
+ // only the low byte is the result of the indirect calculation.
if(!(registers_.direct&0xff)) {
+ data_address_ = (
+ ((registers_.direct + registers_.x.full + instruction_buffer_.value) & registers_.e_masks[1]) +
+ (registers_.direct & registers_.e_masks[0])
+ ) & 0xffff;
++next_op_;
+ } else {
+ data_address_ = (
+ registers_.direct + registers_.x.full + instruction_buffer_.value
+ ) & 0xffff;
}
+ data_address_increment_mask_ = 0x00'ff'ff;
continue;
case OperationConstructDirectIndirectIndexedLong:
From 5d45aa4a6a6e8e820c0b1708aee9886ab6287475 Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Fri, 28 Jul 2023 13:58:01 -0400
Subject: [PATCH 04/14] Fix seed per test.
---
OSBindings/Mac/Clock SignalTests/65816ComparativeTests.mm | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/OSBindings/Mac/Clock SignalTests/65816ComparativeTests.mm b/OSBindings/Mac/Clock SignalTests/65816ComparativeTests.mm
index c342889a6..6017f35ac 100644
--- a/OSBindings/Mac/Clock SignalTests/65816ComparativeTests.mm
+++ b/OSBindings/Mac/Clock SignalTests/65816ComparativeTests.mm
@@ -155,14 +155,14 @@ void print_ram(FILE *file, const std::unordered_map<uint32_t, uint8_t> &data) {
- (void)generate {
BusHandler handler;
- // Make tests repeatable, at least for any given instance of
- // the runtime.
- srand(65816);
-
NSString *const tempDir = NSTemporaryDirectory();
NSLog(@"Outputting to %@", tempDir);
for(int operation = 0; operation < 512; operation++) {
+ // Make tests repeatable, at least for any given instance of
+ // the runtime.
+ srand(65816 + operation);
+
const bool is_emulated = operation & 256;
const uint8_t opcode = operation & 255;
From 3a02c22072d918fd43e8f134c5c0c9fb502fcced Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Sun, 30 Jul 2023 16:25:51 -0400
Subject: [PATCH 05/14] Provide an always-16bit-address route to the stack.
---
.../65816/Implementation/65816Implementation.hpp | 14 ++++++++++++++
Processors/65816/Implementation/65816Storage.hpp | 5 +++++
2 files changed, 19 insertions(+)
diff --git a/Processors/65816/Implementation/65816Implementation.hpp b/Processors/65816/Implementation/65816Implementation.hpp
index c11705c1b..9bd0b8902 100644
--- a/Processors/65816/Implementation/65816Implementation.hpp
+++ b/Processors/65816/Implementation/65816Implementation.hpp
@@ -191,6 +191,13 @@ template <typename BusHandler, bool uses_ready_line> void Processor<BusHandler,
--registers_.s.full;
break;
+ case CyclePushNotEmulation:
+ bus_address_ = registers_.s.full;
+ bus_value_ = data_buffer_.next_output_descending();
+ bus_operation_ = MOS6502Esque::Write;
+ --registers_.s.full;
+ break;
+
case CyclePullIfNotEmulation:
if(registers_.emulation_flag) {
continue;
@@ -202,6 +209,13 @@ template <typename BusHandler, bool uses_ready_line> void Processor<BusHandler,
stack_access(data_buffer_.next_input(), MOS6502Esque::Read);
break;
+ case CyclePullNotEmulation:
+ ++registers_.s.full;
+ bus_address_ = registers_.s.full;
+ bus_value_ = data_buffer_.next_input();
+ bus_operation_ = MOS6502Esque::Read;
+ break;
+
case CycleAccessStack:
stack_access(&bus_throwaway_, MOS6502Esque::InternalOperationRead);
break;
diff --git a/Processors/65816/Implementation/65816Storage.hpp b/Processors/65816/Implementation/65816Storage.hpp
index 35d4570b6..d227dd899 100644
--- a/Processors/65816/Implementation/65816Storage.hpp
+++ b/Processors/65816/Implementation/65816Storage.hpp
@@ -58,6 +58,11 @@ enum MicroOp: uint8_t {
/// Performs as CyclePull if the 65816 is not in emulation mode; otherwise skips itself.
CyclePullIfNotEmulation,
+ /// Pushes a single byte from the data buffer to the stack, always using its full 16-bit address.
+ CyclePushNotEmulation,
+ /// Pulls a single byte to the data buffer from the stack, always using its full 16-bit address.
+ CyclePullNotEmulation,
+
/// Issues a BusOperation::None and regresses the micro-op counter until an established
/// STP or WAI condition is satisfied.
CycleRepeatingNone,
From 2f7dd0b01a55073c1038558c0255625084e937bd Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Sun, 30 Jul 2023 16:26:29 -0400
Subject: [PATCH 06/14] Correct stack behaviour of PLD.
---
Processors/65816/Implementation/65816Storage.cpp | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/Processors/65816/Implementation/65816Storage.cpp b/Processors/65816/Implementation/65816Storage.cpp
index 96aeb08ae..9854df814 100644
--- a/Processors/65816/Implementation/65816Storage.cpp
+++ b/Processors/65816/Implementation/65816Storage.cpp
@@ -656,7 +656,7 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
stack_exception_impl(type, is8bit, target, CycleAccessStack);
}
- // 22b. Stack; s, PLx.
+ // 22b(i). Stack; s, PLx, respecting emulation mode. E.g. PLP.
static void stack_pull(AccessType, bool is8bit, const std::function<void(MicroOp)> &target) {
target(CycleFetchPCThrowaway); // IO.
target(CycleFetchPCThrowaway); // IO.
@@ -667,6 +667,17 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
target(OperationPerform);
}
+ // 22b(ii). Stack; s, PLx, ignoring emulation mode. E.g. PLD.
+ static void stack_pull_no_emulation(AccessType, bool is8bit, const std::function<void(MicroOp)> &target) {
+ target(CycleFetchPCThrowaway); // IO.
+ target(CycleFetchPCThrowaway); // IO.
+
+ if(!is8bit) target(CyclePullNotEmulation); // REG low.
+ target(CyclePullNotEmulation); // REG [high].
+
+ target(OperationPerform);
+ }
+
// 22c. Stack; s, PHx.
static void stack_push(AccessType, bool is8bit, const std::function<void(MicroOp)> &target) {
target(CycleFetchPCThrowaway); // IO.
@@ -852,7 +863,7 @@ ProcessorStorage::ProcessorStorage() {
/* 0x28 PLP s */ op(stack_pull, PLP, AccessMode::Always8Bit);
/* 0x29 AND # */ op(immediate, AND);
/* 0x2a ROL A */ op(accumulator, ROL);
- /* 0x2b PLD s */ op(stack_pull, PLD, AccessMode::Always16Bit);
+ /* 0x2b PLD s */ op(stack_pull_no_emulation, PLD, AccessMode::Always16Bit);
/* 0x2c BIT a */ op(absolute, BIT);
/* 0x2d AND a */ op(absolute, AND);
/* 0x2e ROL a */ op(absolute_rmw, ROL);
From 3ec61e877046f19bf41cfa6124c446aa7c436384 Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Sun, 30 Jul 2023 16:27:13 -0400
Subject: [PATCH 07/14] Fix stack usage of RTL.
---
Processors/65816/Implementation/65816Storage.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/Processors/65816/Implementation/65816Storage.cpp b/Processors/65816/Implementation/65816Storage.cpp
index 9854df814..dce4ff98f 100644
--- a/Processors/65816/Implementation/65816Storage.cpp
+++ b/Processors/65816/Implementation/65816Storage.cpp
@@ -754,9 +754,9 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
target(CycleFetchPCThrowaway); // IO.
target(CycleFetchPCThrowaway); // IO.
- target(CyclePull); // New PCL.
- target(CyclePull); // New PCH.
- target(CyclePull); // New PBR.
+ target(CyclePullNotEmulation); // New PCL.
+ target(CyclePullNotEmulation); // New PCH.
+ target(CyclePullNotEmulation); // New PBR.
target(OperationPerform); // [RTL]
}
From 3762ee1a630fafc833b916e8a913930bc41a49af Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Sun, 30 Jul 2023 16:29:15 -0400
Subject: [PATCH 08/14] Fix stack usage of PHD.
---
Processors/65816/Implementation/65816Storage.cpp | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/Processors/65816/Implementation/65816Storage.cpp b/Processors/65816/Implementation/65816Storage.cpp
index dce4ff98f..df9dfcd75 100644
--- a/Processors/65816/Implementation/65816Storage.cpp
+++ b/Processors/65816/Implementation/65816Storage.cpp
@@ -667,7 +667,7 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
target(OperationPerform);
}
- // 22b(ii). Stack; s, PLx, ignoring emulation mode. E.g. PLD.
+ // 22b(ii). Stack; s, PLx, ignoring emulation mode. I.e. PLD.
static void stack_pull_no_emulation(AccessType, bool is8bit, const std::function<void(MicroOp)> &target) {
target(CycleFetchPCThrowaway); // IO.
target(CycleFetchPCThrowaway); // IO.
@@ -678,7 +678,7 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
target(OperationPerform);
}
- // 22c. Stack; s, PHx.
+ // 22c(i). Stack; s, PHx, respecting emulation mode. E.g. PHP.
static void stack_push(AccessType, bool is8bit, const std::function<void(MicroOp)> &target) {
target(CycleFetchPCThrowaway); // IO.
@@ -688,6 +688,16 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
target(CyclePush); // REG [low].
}
+ // 22c(i). Stack; s, PHx, ignoring emulation mode. I.e. PHD.
+ static void stack_push_no_emulation(AccessType, bool is8bit, const std::function<void(MicroOp)> &target) {
+ target(CycleFetchPCThrowaway); // IO.
+
+ target(OperationPerform);
+
+ if(!is8bit) target(CyclePushNotEmulation); // REG high.
+ target(CyclePushNotEmulation); // REG [low].
+ }
+
// 22d. Stack; s, PEA.
static void stack_pea(AccessType, bool, const std::function<void(MicroOp)> &target) {
target(CycleFetchIncrementPC); // AAL.
@@ -829,7 +839,7 @@ ProcessorStorage::ProcessorStorage() {
/* 0x08 PHP s */ op(stack_push, PHP, AccessMode::Always8Bit);
/* 0x09 ORA # */ op(immediate, ORA);
/* 0x0a ASL A */ op(accumulator, ASL);
- /* 0x0b PHD s */ op(stack_push, PHD, AccessMode::Always16Bit);
+ /* 0x0b PHD s */ op(stack_push_no_emulation, PHD, AccessMode::Always16Bit);
/* 0x0c TSB a */ op(absolute_rmw, TSB);
/* 0x0d ORA a */ op(absolute, ORA);
/* 0x0e ASL a */ op(absolute_rmw, ASL);
From a02b8222faea0cb083a5f42df67d004af8a458f2 Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Sun, 30 Jul 2023 16:29:56 -0400
Subject: [PATCH 09/14] Fix stack usage of PER.
---
Processors/65816/Implementation/65816Storage.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Processors/65816/Implementation/65816Storage.cpp b/Processors/65816/Implementation/65816Storage.cpp
index df9dfcd75..72651a19e 100644
--- a/Processors/65816/Implementation/65816Storage.cpp
+++ b/Processors/65816/Implementation/65816Storage.cpp
@@ -730,8 +730,8 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
target(OperationConstructPER);
- target(CyclePush); // AAH.
- target(CyclePush); // AAL.
+ target(CyclePushNotEmulation); // AAH.
+ target(CyclePushNotEmulation); // AAL.
}
// 22g. Stack; s, RTI.
From e52d1866ab3ef59e1df9919d21a2bb9d2925877a Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Sun, 30 Jul 2023 16:32:56 -0400
Subject: [PATCH 10/14] Fix PEI stack usage.
---
Processors/65816/Implementation/65816Storage.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Processors/65816/Implementation/65816Storage.cpp b/Processors/65816/Implementation/65816Storage.cpp
index 72651a19e..399a3033f 100644
--- a/Processors/65816/Implementation/65816Storage.cpp
+++ b/Processors/65816/Implementation/65816Storage.cpp
@@ -718,8 +718,8 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
target(CycleFetchIncrementData); // AAL.
target(CycleFetchData); // AAH.
- target(CyclePush); // AAH.
- target(CyclePush); // AAL.
+ target(CyclePushNotEmulation); // AAH.
+ target(CyclePushNotEmulation); // AAL.
}
// 22f. Stack; s, PER.
From 9f1a657cc49d67bf9d8fbcd10ec26101fbb60596 Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Sun, 30 Jul 2023 16:33:44 -0400
Subject: [PATCH 11/14] Fix stack usage of PEA.
---
Processors/65816/Implementation/65816Storage.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Processors/65816/Implementation/65816Storage.cpp b/Processors/65816/Implementation/65816Storage.cpp
index 399a3033f..b01973a36 100644
--- a/Processors/65816/Implementation/65816Storage.cpp
+++ b/Processors/65816/Implementation/65816Storage.cpp
@@ -705,8 +705,8 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
target(OperationCopyInstructionToData);
- target(CyclePush); // AAH.
- target(CyclePush); // AAL.
+ target(CyclePushNotEmulation); // AAH.
+ target(CyclePushNotEmulation); // AAL.
}
// 22e. Stack; s, PEI.
From acd7f9f4cd2e4dcf5e414b8283d743e96439cacb Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Sun, 30 Jul 2023 16:34:42 -0400
Subject: [PATCH 12/14] Fix stack usage of JSL.
---
Processors/65816/Implementation/65816Storage.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/Processors/65816/Implementation/65816Storage.cpp b/Processors/65816/Implementation/65816Storage.cpp
index b01973a36..a901229b1 100644
--- a/Processors/65816/Implementation/65816Storage.cpp
+++ b/Processors/65816/Implementation/65816Storage.cpp
@@ -319,7 +319,7 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
target(CycleFetchIncrementPC); // New PCH.
target(OperationCopyPBRToData); // Copy PBR to the data register.
- target(CyclePush); // PBR.
+ target(CyclePushNotEmulation); // PBR.
target(CycleFetchPreviousThrowaway); // IO.
target(CycleFetchPC); // New PBR.
@@ -327,8 +327,8 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
target(OperationConstructAbsolute); // Calculate data address.
target(OperationPerform); // [JSL]
- target(CyclePush); // PCH.
- target(CyclePush); // PCL.
+ target(CyclePushNotEmulation); // PCH.
+ target(CyclePushNotEmulation); // PCL.
}
// 5. Absolute long, X; al, x.
From e61a4eb5a9431a91442ad1d3e383f5a4db8e66c7 Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Sun, 30 Jul 2023 16:36:29 -0400
Subject: [PATCH 13/14] Regularise PHD and PLD.
---
Processors/65816/Implementation/65816Storage.cpp | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/Processors/65816/Implementation/65816Storage.cpp b/Processors/65816/Implementation/65816Storage.cpp
index a901229b1..99be184ed 100644
--- a/Processors/65816/Implementation/65816Storage.cpp
+++ b/Processors/65816/Implementation/65816Storage.cpp
@@ -668,12 +668,12 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
}
// 22b(ii). Stack; s, PLx, ignoring emulation mode. I.e. PLD.
- static void stack_pull_no_emulation(AccessType, bool is8bit, const std::function<void(MicroOp)> &target) {
+ static void stack_pld(AccessType, bool, const std::function<void(MicroOp)> &target) {
target(CycleFetchPCThrowaway); // IO.
target(CycleFetchPCThrowaway); // IO.
- if(!is8bit) target(CyclePullNotEmulation); // REG low.
- target(CyclePullNotEmulation); // REG [high].
+ target(CyclePullNotEmulation); // REG low.
+ target(CyclePullNotEmulation); // REG [high].
target(OperationPerform);
}
@@ -689,13 +689,13 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
}
// 22c(i). Stack; s, PHx, ignoring emulation mode. I.e. PHD.
- static void stack_push_no_emulation(AccessType, bool is8bit, const std::function<void(MicroOp)> &target) {
+ static void stack_phd(AccessType, bool, const std::function<void(MicroOp)> &target) {
target(CycleFetchPCThrowaway); // IO.
target(OperationPerform);
- if(!is8bit) target(CyclePushNotEmulation); // REG high.
- target(CyclePushNotEmulation); // REG [low].
+ target(CyclePushNotEmulation); // REG high.
+ target(CyclePushNotEmulation); // REG [low].
}
// 22d. Stack; s, PEA.
@@ -839,7 +839,7 @@ ProcessorStorage::ProcessorStorage() {
/* 0x08 PHP s */ op(stack_push, PHP, AccessMode::Always8Bit);
/* 0x09 ORA # */ op(immediate, ORA);
/* 0x0a ASL A */ op(accumulator, ASL);
- /* 0x0b PHD s */ op(stack_push_no_emulation, PHD, AccessMode::Always16Bit);
+ /* 0x0b PHD s */ op(stack_phd, PHD);
/* 0x0c TSB a */ op(absolute_rmw, TSB);
/* 0x0d ORA a */ op(absolute, ORA);
/* 0x0e ASL a */ op(absolute_rmw, ASL);
@@ -873,7 +873,7 @@ ProcessorStorage::ProcessorStorage() {
/* 0x28 PLP s */ op(stack_pull, PLP, AccessMode::Always8Bit);
/* 0x29 AND # */ op(immediate, AND);
/* 0x2a ROL A */ op(accumulator, ROL);
- /* 0x2b PLD s */ op(stack_pull_no_emulation, PLD, AccessMode::Always16Bit);
+ /* 0x2b PLD s */ op(stack_pld, PLD);
/* 0x2c BIT a */ op(absolute, BIT);
/* 0x2d AND a */ op(absolute, AND);
/* 0x2e ROL a */ op(absolute_rmw, ROL);
From 226272501066a3cf385af38609a1d301268d89ff Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Mon, 31 Jul 2023 17:08:02 -0400
Subject: [PATCH 14/14] Reveal 16-bit stack pointer when asked, regardless of
mode.
---
Processors/65816/Implementation/65816Base.cpp | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/Processors/65816/Implementation/65816Base.cpp b/Processors/65816/Implementation/65816Base.cpp
index 83bb01701..3eaf614cd 100644
--- a/Processors/65816/Implementation/65816Base.cpp
+++ b/Processors/65816/Implementation/65816Base.cpp
@@ -14,10 +14,7 @@ uint16_t ProcessorBase::value_of(Register r) const {
switch (r) {
case Register::ProgramCounter: return registers_.pc;
case Register::LastOperationAddress: return last_operation_pc_;
- case Register::StackPointer:
- return
- (registers_.s.full & (registers_.emulation_flag ? 0xff : 0xffff)) |
- (registers_.emulation_flag ? 0x100 : 0x000);
+ case Register::StackPointer: return registers_.s.full;
case Register::Flags: return get_flags();
case Register::A: return registers_.a.full;
case Register::X: return registers_.x.full;