6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-06-30 22:29:56 +00:00
Code Issues Projects Releases Wiki Activity

Restore proper VDP selection.

Browse Source
This commit is contained in:
Thomas Harte 2022-12-31 21:54:14 -05:00
parent ffb0b2ce0b
commit e8aab1fd2a
1 changed files with 14 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
Machines/MasterSystem/MasterSystem.cpp
View File

@ -29,6 +29,7 @@
#include "../../Analyser/Static/Sega/Target.hpp"
#include <algorithm>
#include <cassert>
#include <iostream>
namespace {
@ -77,7 +78,7 @@ class Joystick: public Inputs::ConcreteJoystick {
uint8_t state_ = 0xff;
};
class ConcreteMachine:
template <Analyser::Static::Sega::Target::Model model> class ConcreteMachine:
public Machine,
public CPU::Z80::BusHandler,
public MachineTypes::TimedMachine,
@ -90,7 +91,6 @@ class ConcreteMachine:
public:
ConcreteMachine(const Analyser::Static::Sega::Target &target, const ROMMachine::ROMFetcher &rom_fetcher) :
model_(target.model),
region_(target.region),
paging_scheme_(target.paging_scheme),
z80_(*this),
@ -158,7 +158,7 @@ class ConcreteMachine:
page_cartridge();
// Map RAM.
if(is_master_system(model_)) {
if constexpr (is_master_system(model)) {
map(read_pointers_, ram_, 8*1024, 0xc000, 0x10000);
map(write_pointers_, ram_, 8*1024, 0xc000, 0x10000);
} else {
@ -310,7 +310,7 @@ class ConcreteMachine:
case CPU::Z80::PartialMachineCycle::Output:
switch(address & 0xc1) {
case 0x00: // i.e. even ports less than 0x40.
if(is_master_system(model_)) {
if constexpr (is_master_system(model)) {
// TODO: Obey the RAM enable.
LOG("Memory control: " << PADHEX(2) << memory_control_);
memory_control_ = *cycle.value;
@ -430,8 +430,7 @@ class ConcreteMachine:
}
private:
// TODO: incorporate this into the VDP declaration.
static TI::TMS::Personality tms_personality_for_model(Analyser::Static::Sega::Target::Model model) {
static constexpr TI::TMS::Personality tms_personality() {
switch(model) {
default:
case Target::Model::SG1000: return TI::TMS::TMS9918A;
@ -481,11 +480,10 @@ class ConcreteMachine:
}
using Target = Analyser::Static::Sega::Target;
const Target::Model model_;
const Target::Region region_;
const Target::PagingScheme paging_scheme_;
CPU::Z80::Processor<ConcreteMachine, false, false> z80_;
JustInTimeActor<TI::TMS::TMS9918<TI::TMS::Personality::SMSVDP>> vdp_; // TODO: use tms_personality_for_model
JustInTimeActor<TI::TMS::TMS9918<tms_personality()>> vdp_;
Concurrency::AsyncTaskQueue<false> audio_queue_;
TI::SN76489 sn76489_;
@ -559,7 +557,14 @@ using namespace Sega::MasterSystem;
Machine *Machine::MasterSystem(const Analyser::Static::Target *target, const ROMMachine::ROMFetcher &rom_fetcher) {
using Target = Analyser::Static::Sega::Target;
const Target *const sega_target = dynamic_cast<const Target *>(target);
return new ConcreteMachine(*sega_target, rom_fetcher);
switch(sega_target->model) {
case Target::Model::SG1000: return new ConcreteMachine<Target::Model::SG1000>(*sega_target, rom_fetcher);
case Target::Model::MasterSystem: return new ConcreteMachine<Target::Model::MasterSystem>(*sega_target, rom_fetcher);
case Target::Model::MasterSystem2: return new ConcreteMachine<Target::Model::MasterSystem2>(*sega_target, rom_fetcher);
default:
assert(false);
}
}
Machine::~Machine() {}