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Added a test on LD A, (DE) and LD A, (BC), and adjusted implementation to pass.

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This commit is contained in:
Thomas Harte 2017-07-22 11:20:21 -04:00
parent d51b66c204
commit eaf313b0f6
2 changed files with 25 additions and 3 deletions
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24
OSBindings/Mac/Clock SignalTests/Z80MemptrTests.swift
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@ -23,7 +23,7 @@ class Z80MemptrTests: XCTestCase {
return machine.value(for: .memPtr) return machine.value(for: .memPtr)
} }
// LD A,(addr) // LD A, (addr)
func testLDAnn() { func testLDAnn() {
var program: [UInt8] = [ var program: [UInt8] = [
0x3a, 0x00, 0x00 0x3a, 0x00, 0x00
@ -38,4 +38,26 @@ class Z80MemptrTests: XCTestCase {
} }
} }
// LD A, (rp)
func testLDArp() {
let bcProgram: [UInt8] = [
0x0a
]
let deProgram: [UInt8] = [
0x1a
]
for addr in 0 ..< 65536 {
machine.setValue(UInt16(addr), for: .BC)
machine.setValue(UInt16(addr), for: .DE)
let expectedResult = UInt16((addr + 1) & 0xffff)
let bcResult = test(program: bcProgram, length: 7, initialValue: 0xffff)
let deResult = test(program: deProgram, length: 7, initialValue: 0xffff)
XCTAssertEqual(bcResult, expectedResult)
XCTAssertEqual(deResult, expectedResult)
}
}
} }

4
Processors/Z80/Z80.hpp
View File

@ -574,7 +574,7 @@ template <class T> class Processor {
/* 0x07 RLCA */ StdInstr({MicroOp::RLCA}), /* 0x07 RLCA */ StdInstr({MicroOp::RLCA}),
/* 0x08 EX AF, AF' */ StdInstr({MicroOp::ExAFAFDash}), /* 0x09 ADD HL, BC */ ADD16(index, bc_), /* 0x08 EX AF, AF' */ StdInstr({MicroOp::ExAFAFDash}), /* 0x09 ADD HL, BC */ ADD16(index, bc_),
/* 0x0a LD A, (BC) */ StdInstr({MicroOp::Move16, &bc_.full, &memptr_.full}, Read3(memptr_, a_)), /* 0x0a LD A, (BC) */ StdInstr({MicroOp::Move16, &bc_.full, &memptr_.full}, Read3(memptr_, a_), Inc16(memptr_)),
/* 0x0b DEC BC; 0x0c INC C; 0x0d DEC C; 0x0e LD C, n */ /* 0x0b DEC BC; 0x0c INC C; 0x0d DEC C; 0x0e LD C, n */
DEC_INC_DEC_LD(bc_, bc_.bytes.low), DEC_INC_DEC_LD(bc_, bc_.bytes.low),
@ -590,7 +590,7 @@ template <class T> class Processor {
/* 0x17 RLA */ StdInstr({MicroOp::RLA}), /* 0x17 RLA */ StdInstr({MicroOp::RLA}),
/* 0x18 JR */ StdInstr(ReadInc(pc_, temp8_), InternalOperation(5), {MicroOp::CalculateIndexAddress, &pc_.full}, {MicroOp::Move16, &memptr_.full, &pc_.full}), /* 0x18 JR */ StdInstr(ReadInc(pc_, temp8_), InternalOperation(5), {MicroOp::CalculateIndexAddress, &pc_.full}, {MicroOp::Move16, &memptr_.full, &pc_.full}),
/* 0x19 ADD HL, DE */ ADD16(index, de_), /* 0x19 ADD HL, DE */ ADD16(index, de_),
/* 0x1a LD A, (DE) */ StdInstr({MicroOp::Move16, &de_.full, &memptr_.full}, Read3(memptr_, a_)), /* 0x1a LD A, (DE) */ StdInstr({MicroOp::Move16, &de_.full, &memptr_.full}, Read3(memptr_, a_), Inc16(memptr_)),
/* 0x1b DEC DE; 0x1c INC E; 0x1d DEC E; 0x1e LD E, n */ /* 0x1b DEC DE; 0x1c INC E; 0x1d DEC E; 0x1e LD E, n */
DEC_INC_DEC_LD(de_, de_.bytes.low), DEC_INC_DEC_LD(de_, de_.bytes.low),