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Ensures the AY stops listening to the bus after each read or write.
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@ -132,6 +132,7 @@ class ConcreteMachine:
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ay_->run_for(time_since_ay_update_.divide_cycles(Cycles(2)));
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ay_->set_control_lines(static_cast<GI::AY38910::ControlLines>(GI::AY38910::BC2 | GI::AY38910::BC1));
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*cycle.value = ay_->get_data_output();
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ay_->set_control_lines(static_cast<GI::AY38910::ControlLines>(0));
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break;
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case 0xa8: case 0xa9:
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@ -145,8 +146,9 @@ class ConcreteMachine:
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}
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break;
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case CPU::Z80::PartialMachineCycle::Output:
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switch(address & 0xff) {
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case CPU::Z80::PartialMachineCycle::Output: {
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const int port = address & 0xff;
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switch(port) {
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case 0x98: case 0x99:
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vdp_->run_for(time_since_vdp_update_.flush());
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vdp_->set_register(address, *cycle.value);
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@ -154,16 +156,11 @@ class ConcreteMachine:
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time_until_interrupt_ = vdp_->get_time_until_interrupt();
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break;
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case 0xa0:
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case 0xa0: case 0xa1:
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ay_->run_for(time_since_ay_update_.divide_cycles(Cycles(2)));
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ay_->set_control_lines(static_cast<GI::AY38910::ControlLines>(GI::AY38910::BDIR | GI::AY38910::BC2 | GI::AY38910::BC1));
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ay_->set_data_input(*cycle.value);
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break;
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case 0xa1:
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ay_->run_for(time_since_ay_update_.divide_cycles(Cycles(2)));
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ay_->set_control_lines(static_cast<GI::AY38910::ControlLines>(GI::AY38910::BDIR | GI::AY38910::BC2));
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ay_->set_control_lines(static_cast<GI::AY38910::ControlLines>(GI::AY38910::BDIR | GI::AY38910::BC2 | ((port == 0xa0) ? GI::AY38910::BC1 : 0)));
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ay_->set_data_input(*cycle.value);
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ay_->set_control_lines(static_cast<GI::AY38910::ControlLines>(0));
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break;
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case 0xa8: case 0xa9:
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@ -171,7 +168,7 @@ class ConcreteMachine:
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i8255_.set_register(address, *cycle.value);
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break;
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}
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break;
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} break;
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default: break;
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}
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