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mirror of https://github.com/TomHarte/CLK.git synced 2024-10-01 13:58:20 +00:00

Starts building out a PowerPC decoder.

This commit is contained in:
Thomas Harte 2020-12-30 22:55:59 -05:00
parent 3d79b11f92
commit ed63e7ea75
3 changed files with 284 additions and 0 deletions

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//
// PowerPC.cpp
// Clock Signal
//
// Created by Thomas Harte on 12/30/20.
// Copyright © 2020 Thomas Harte. All rights reserved.
//
#include "PowerPC.hpp"
using namespace CPU::Decoder::PowerPC;
Decoder::Decoder(Model model) : model_(model) {}
Instruction Decoder::decode(uint32_t opcode) {
switch(opcode >> 26) {
case 31:
const uint8_t dest = (opcode >> 21) & 0x1f;
const uint8_t a = (opcode >> 16) & 0x1f;
const uint8_t b = (opcode >> 11) & 0x1f;
#define OECase(x) case x: case 0x200 + x
switch((opcode >> 1) & 0x3ff) {
case 0:
// cmp; 601 10-26
break;
case 4:
// tw; 601 10-214
break;
OECase(8):
// subfcx; 601 10-207
break;
// case 9:
// // mulhdux
// break;
OECase(10):
// addcx; 601 10-9
break;
case 11:
// mulhwux; 601 10-142
break;
case 19:
// mfcr; 601 10-122
break;
case 20:
// lwarx
break;
case 21:
// ldx
break;
// lwzx
// slwx
// cntlzwx
// sldx
// andx
// ampl
// subfx
// ldux
// dcbst
// lwzux
// cntlzdx
// andcx
// td
// mulhx
// mulhwx
// mfmsr
// ldarx
// dcbf
// lbzx
// negx
// norx
// subfex
// adex
// mtcrf
// mtmsr
// stfx
// stwcx.
// stwx
// stdux
// stwux
// subfzex
// addzex
// mtsr
// stdcx.
// stbx
// subfmex
// mulld
// addmex
// mullwx
// mtsrin
// scbtst
// stbux
// addx
// dcbt
// lhzx
// eqvx
// tlbie
// eciwx
// lhzux
// xorx
// mfspr
// lwax
// lhax
// lbia
// mftb
// lwaux
// lhaux
// sthx
// orcx
// sradix
// slbie
// ecowx
// sthux
// orx
// divdux
// divwux
// mtspr
// dcbi
// nandx
// divdx
// divwx
// slbia
// mcrxr
// lswx
// lwbrx
// lfsx
// srwx
// srdx
// tlbsync
// lfsux
// mfsr
// lswi
// sync
// lfdx
// lfdux
// mfsrin
// stswx
// stwbrx
// stfsx
// stfsux
// stswi
// stfdx
// stfdux
// lhbrx
// srawx
// sradx
// srawix
// eieio
// ethbrx
// extshx
// extsbx
// lcbi
// stfiwx
// extsw
// dcbz
OECase(138):
// addex
break;
OECase(266):
// addx
break;
case 28:
// andx
break;
case 60:
// andcx
break;
}
#undef OECase
break;
}
return Instruction();
}

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@ -0,0 +1,86 @@
//
// PowerPC.hpp
// Clock Signal
//
// Created by Thomas Harte on 12/30/20.
// Copyright © 2020 Thomas Harte. All rights reserved.
//
#ifndef PowerPC_hpp
#define PowerPC_hpp
#include <cstdint>
namespace CPU {
namespace Decoder {
namespace PowerPC {
enum class Model {
MPC601,
};
// TODO: complete the following table.
enum class Operation: uint8_t {
Undefined,
// These 601-exclusive instructions; a lot of them are carry-overs
// from POWER.
absx, clcs, divx, divsx, dozx, dozi, lscbxx, maskgx, maskirx, mulx,
nabsx, rlmix, rribx, slex, sleqx, sliqx, slliqx, sllqx, slqx,
sraiqx, sraqx, srex, sreax, sreqx, sriqx, srliqx, srlqx, srqx,
// 32- and 64-bit PowerPC instructions.
addx, addcx, addex, addi, addic, addic_, addis, addmex, addzex, andx,
andcx, andi_, andis_, bx, bcx, bcctrx, bclrx, cmp, cmpi, cmpl, cmpli,
cntlzwx, crand, crandc, creqv, crnand, crnor, cror, crorc, crxor, dcbf,
dcbst, dcbt, dcbtst, dcbz, divwx, divwux, eciwx, ecowx, eieio, eqvx,
extsbx, extshx, fabsx, faddx, faddsx, fcmpo, fcmpu, fctiwx, fctiwzx,
fdivx, fdivsx, fmaddx, fmaddsx, fmrx, fmsubx, fmsubsx, fmulx, fmulsx,
fnabsx, fnegx, fnmaddx, fnmaddsx, fnmsubx, fnmsubsx, frspx, fsubx, fsubsx,
icbi, isync, lbz, lbzu, lbzux, lbzx, lfd, lfdu, lfdux, lfdx, lfs, lfsu,
lfsux, lfsx, lha, lhau, lhaux, lhax, lhbrx, lhz, lhzu, lhzux, lhzx, lmw,
lswi, lswx, lwarx, lwbrx, lwz, lwzu, lwzux, lwzx, mcrf, mcrfs, mcrxr,
mfcr, mffsx, mfmsr, mfspr, mfsr, mfsrin, mtcrf, mtfsb0x, mtfsb1x, mtfsfx,
mtfsfix, mtmsr, mtspr, mtsr, mtsrin, mulhwx, mulhwux, mulli, mullwx,
nandx, negx, norx, orx, orcx, ori, oris, rfi, rlwimix, rlwinmx, rlwnmx,
sc, slwx, srawx, srawix, srwx, stb, stbu, stbux, stbx, stfd, stfdu,
stfdux, stfdx, stfs, stfsu, stfsux, stfsx, sth, sthbrx, sthu, sthux, sthx,
stmw, stswi, stswx, stw, stwbrx, stwcx_, stwu, stwux, stwx, subfx, subfcx,
subfex, subfic, subfmex, subfzex, sync, tlbie, tw, twi, xorx, xori, xoris,
// 32-bit, supervisor level.
dcbi,
// Optional.
fresx, frsqrtex, fselx, fsqrtx, frsqrtsx, slbia, slbie,
// 64-bit only PowerPC instructions.
cntlzdx, divdx, divdux, extswx, fcfidx, fctidx, fctidzx
};
struct Instruction {
Operation operation = Operation::Undefined;
//
Instruction() {}
Instruction(Operation operation) : operation(operation) {}
};
struct Decoder {
public:
Decoder(Model model);
Instruction decode(uint32_t opcode);
private:
Model model_;
};
}
}
}
#include <stdio.h>
#endif /* PowerPC_hpp */