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Implements MOVE to CCR.
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Thomas Harte
parent
652f4ebfed
commit
eda88cc462
@ -6,24 +6,32 @@
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// Copyright © 2019 Thomas Harte. All rights reserved.
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//
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#define get_status() \
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#define get_ccr() \
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( \
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(carry_flag_ ? 0x0001 : 0x0000) | \
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(overflow_flag_ ? 0x0002 : 0x0000) | \
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(zero_result_ ? 0x0000 : 0x0004) | \
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(negative_flag_ ? 0x0008 : 0x0000) | \
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(extend_flag_ ? 0x0010 : 0x0000) | \
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(extend_flag_ ? 0x0010 : 0x0000) \
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)
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#define get_status() \
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( \
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get_ccr() | \
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(interrupt_level_ << 8) | \
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(trace_flag_ ? 0x8000 : 0x0000) | \
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(is_supervisor_ << 13) \
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)
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#define set_status(x) \
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#define set_ccr(x) \
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carry_flag_ = (x) & 0x0001; \
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overflow_flag_ = (x) & 0x0002; \
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zero_result_ = ((x) & 0x0004) ^ 0x0004; \
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negative_flag_ = (x) & 0x0008; \
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extend_flag_ = (x) & 0x0010; \
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extend_flag_ = (x) & 0x0010;
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#define set_status(x) \
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set_ccr(x) \
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interrupt_level_ = ((x) >> 8) & 7; \
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trace_flag_ = (x) & 0x8000; \
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set_is_supervisor(!!(((x) >> 13) & 1));
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@ -58,9 +66,6 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
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active_micro_op_ = active_program_->micro_operations;
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}
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#define sub_overflow() (source ^ destination) & (destination ^ result)
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#define add_overflow() ~(source ^ destination) & (destination ^ result)
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switch(active_micro_op_->action) {
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default:
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std::cerr << "Unhandled 68000 micro op action " << std::hex << active_micro_op_->action << std::endl;
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@ -69,6 +74,8 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
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case int(MicroOp::Action::None): break;
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case int(MicroOp::Action::PerformOperation):
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#define sub_overflow() (source ^ destination) & (destination ^ result)
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#define add_overflow() ~(source ^ destination) & (destination ^ result)
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switch(active_program_->operation) {
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/*
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ABCD adds the lowest bytes form the source and destination using BCD arithmetic,
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@ -332,6 +339,10 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
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active_program_->source->halves.low.full = get_status();
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break;
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case Operation::MOVEtoCCR:
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set_ccr(active_program_->source->full);
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break;
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/*
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NEGs: negatives the destination, setting the zero,
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negative, overflow and carry flags appropriate, and extend.
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@ -403,9 +414,9 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
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const int source = 0;
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const int destination = active_program_->destination->full;
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int64_t result = source - destination - (extend_flag_ ? 1 : 0);
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active_program_->destination->full = result;
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active_program_->destination->full = uint32_t(result);
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zero_result_ = result;
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zero_result_ = uint_fast32_t(result);
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extend_flag_ = carry_flag_ = result >> 32;
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negative_flag_ = result & 0x80000000;
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overflow_flag_ = sub_overflow() & 0x80000000;
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@ -456,7 +467,7 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
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zero_result_ |= result & 0xff;
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extend_flag_ = carry_flag_ = result & ~0xff;
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negative_flag_ = result & 0x80;
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overflow_flag_ = (source ^ destination) & (destination ^ result) & 0x80;
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overflow_flag_ = sub_overflow() & 0x80;
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// Store the result.
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active_program_->destination->halves.low.halves.low = uint8_t(result);
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@ -470,7 +481,7 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
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zero_result_ = active_program_->destination->halves.low.halves.low = uint8_t(result);
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extend_flag_ = carry_flag_ = result & ~0xff;
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negative_flag_ = result & 0x80;
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overflow_flag_ = (source ^ destination) & (destination ^ result) & 0x80;
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overflow_flag_ = sub_overflow() & 0x80;
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} break;
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case Operation::SUBw: {
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@ -481,7 +492,7 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
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zero_result_ = active_program_->destination->halves.low.full = uint16_t(result);
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extend_flag_ = carry_flag_ = result & ~0xffff;
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negative_flag_ = result & 0x8000;
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overflow_flag_ = (source ^ destination) & (destination ^ result) & 0x8000;
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overflow_flag_ = sub_overflow() & 0x8000;
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} break;
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case Operation::SUBl: {
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@ -492,7 +503,7 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
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zero_result_ = active_program_->destination->halves.low.full = uint32_t(result);
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extend_flag_ = carry_flag_ = result >> 32;
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negative_flag_ = result & 0x80000000;
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overflow_flag_ = (source ^ destination) & (destination ^ result) & 0x80000000;
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overflow_flag_ = sub_overflow() & 0x80000000;
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} break;
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case Operation::SUBAw:
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@ -510,6 +521,8 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
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std::cerr << "Should do something with program operation " << int(active_program_->operation) << std::endl;
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break;
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}
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#undef sub_overflow
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#undef add_overflow
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break;
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case int(MicroOp::Action::SetMoveFlagsb):
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@ -775,3 +788,5 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
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#undef get_status
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#undef set_status
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#undef set_ccr
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#undef get_ccr
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@ -256,7 +256,7 @@ struct ProcessorStorageConstructor {
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enum class Decoder {
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Decimal,
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MOVE, // twelve lowest bits are register, mode, mode, register, for destination and source respectively.
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MOVEtoSR, // six lowest bits are [mode, register], decoding to MOVE SR
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MOVEtoSRCCR, // six lowest bits are [mode, register], decoding to MOVE SR/CCR
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CMPI, // eight lowest bits are [size, mode, register], decoding to CMPI
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BRA, // eight lowest bits are ignored, and an 'n np np' is scheduled
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Bcc, // twelve lowest bits are ignored, only a PerformAction is scheduled
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@ -309,7 +309,8 @@ struct ProcessorStorageConstructor {
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{0xf000, 0x2000, Operation::MOVEl, Decoder::MOVE}, // 4-116 (p220)
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{0xf000, 0x3000, Operation::MOVEw, Decoder::MOVE}, // 4-116 (p220)
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{0xffc0, 0x46c0, Operation::MOVEtoSR, Decoder::MOVEtoSR}, // 6-19 (p473)
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{0xffc0, 0x46c0, Operation::MOVEtoSR, Decoder::MOVEtoSRCCR}, // 6-19 (p473)
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{0xffc0, 0x44c0, Operation::MOVEtoCCR, Decoder::MOVEtoSRCCR}, // 4-123 (p227)
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{0xf1c0, 0xb000, Operation::CMPb, Decoder::CMP}, // 4-75 (p179)
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{0xf1c0, 0xb040, Operation::CMPw, Decoder::CMP}, // 4-75 (p179)
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@ -1245,10 +1246,10 @@ struct ProcessorStorageConstructor {
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}
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} break;
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case Decoder::MOVEtoSR: {
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case Decoder::MOVEtoSRCCR: {
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if(ea_mode == 1) continue;
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storage_.instructions[instruction].set_source(storage_, ea_mode, ea_register);
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storage_.instructions[instruction].requires_supervisor = true;
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storage_.instructions[instruction].requires_supervisor = (operation == Operation::MOVEtoSR);
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/* DEVIATION FROM YACHT.TXT: it has all of these reading an extra word from the PC;
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this looks like a mistake so I've padded with nil cycles in the middle. */
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@ -55,6 +55,7 @@ class ProcessorStorage {
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MOVEAw, MOVEAl,
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MOVEtoSR, MOVEfromSR,
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MOVEtoCCR,
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CMPb, CMPw, CMPl,
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BTSTb, BTSTl,
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