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Corrects word access order of MOVEM.l.

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This commit is contained in:
Thomas Harte 2019-04-20 15:13:12 -04:00
parent 2cac4b0d74
commit ef33b004f9
2 changed files with 6 additions and 6 deletions
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8
OSBindings/Mac/Clock SignalTests/QLTests.mm
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@ -71,20 +71,20 @@ class QL: public CPU::MC68000::BusHandler {
case Microcycle::SelectWord | Microcycle::Read:
cycle.value->full = is_peripheral ? peripheral_result : base[word_address];
if(!(cycle.operation & Microcycle::IsProgram)) printf("[word r %08x -> %04x]\n ", *cycle.address, cycle.value->full);
if(!(cycle.operation & Microcycle::IsProgram)) printf("\n[word r %08x -> %04x]\t", *cycle.address, cycle.value->full);
break;
case Microcycle::SelectByte | Microcycle::Read:
cycle.value->halves.low = (is_peripheral ? peripheral_result : base[word_address]) >> cycle.byte_shift();
if(!(cycle.operation & Microcycle::IsProgram)) printf("[byte r %08x -> %02x]\n", *cycle.address, cycle.value->halves.low);
if(!(cycle.operation & Microcycle::IsProgram)) printf("\n[byte r %08x -> %02x]\t", *cycle.address, cycle.value->halves.low);
break;
case Microcycle::SelectWord:
assert(!(is_rom && !is_peripheral));
if(!(cycle.operation & Microcycle::IsProgram)) printf("[word w %04x -> %08x]\n", cycle.value->full, *cycle.address);
if(!(cycle.operation & Microcycle::IsProgram)) printf("\n{word w %04x -> %08x}\t", cycle.value->full, *cycle.address);
if(!is_peripheral) base[word_address] = cycle.value->full;
break;
case Microcycle::SelectByte:
assert(!(is_rom && !is_peripheral));
if(!(cycle.operation & Microcycle::IsProgram)) printf("[byte w %02x -> %08x]\n", cycle.value->halves.low, *cycle.address);
if(!(cycle.operation & Microcycle::IsProgram)) printf("\n{byte w %02x -> %08x}\t", cycle.value->halves.low, *cycle.address);
if(!is_peripheral) base[word_address] = (cycle.value->halves.low << cycle.byte_shift()) | (base[word_address] & (0xffff ^ cycle.byte_mask()));
break;
}

4
Processors/68000/Implementation/68000Implementation.hpp
View File

@ -580,8 +580,8 @@ template <class T, bool dtack_is_implicit> void Processor<T, dtack_is_implicit>:
step[2].microcycle.address = step[3].microcycle.address = address_storage + 1; \
\
const auto target = (offset > 7) ? &address_[offset&7] : &data_[offset]; \
step[(l^2)].microcycle.value = step[(l^2)+1].microcycle.value = &target->halves.high; \
step[l].microcycle.value = step[l+1].microcycle.value = &target->halves.low; \
step[l].microcycle.value = step[l+1].microcycle.value = &target->halves.high; \
step[(l^2)].microcycle.value = step[(l^2)+1].microcycle.value = &target->halves.low; \
\
address_storage += 2; \
step += 4; \