diff --git a/InstructionSets/68k/Decoder.cpp b/InstructionSets/68k/Decoder.cpp index ad48bd3cc..1b305a9a1 100644 --- a/InstructionSets/68k/Decoder.cpp +++ b/InstructionSets/68k/Decoder.cpp @@ -411,6 +411,7 @@ template Preinstruction Predecoder::validated case OpT(Operation::DIVU): case OpT(Operation::DIVS): case OpT(Operation::MULU): case OpT(Operation::MULS): + case OpT(Operation::CHK): switch(original.mode<0>()) { default: return original; diff --git a/InstructionSets/68k/Instruction.hpp b/InstructionSets/68k/Instruction.hpp index c1483741b..77d9dc75c 100644 --- a/InstructionSets/68k/Instruction.hpp +++ b/InstructionSets/68k/Instruction.hpp @@ -142,6 +142,7 @@ constexpr int8_t quick(uint16_t instruction) { case Operation::Bccb: case Operation::BSRb: case Operation::MOVEq: return int8_t(instruction); + case Operation::TRAP: return int8_t(instruction & 15); default: { int8_t value = (instruction >> 9) & 7; value |= (value - 1)&8; @@ -151,11 +152,15 @@ constexpr int8_t quick(uint16_t instruction) { } constexpr int8_t quick(Operation op, uint16_t instruction) { - if(op == Operation::MOVEq || op == Operation::Bccb || op == Operation::BSRb) { - return quick(instruction); - } else { - // ADDw is arbitrary; anything other than MOVEq will do. - return quick(instruction); + switch(op) { + case Operation::MOVEq: return quick(instruction); + case Operation::Bccb: return quick(instruction); + case Operation::BSRb: return quick(instruction); + case Operation::TRAP: return quick(instruction); + + default: + // ADDw is arbitrary; anything other than those listed above will do. + return quick(instruction); } } diff --git a/OSBindings/Mac/Clock SignalTests/m68kDecoderTests.mm b/OSBindings/Mac/Clock SignalTests/m68kDecoderTests.mm index 01397129c..9f976e938 100644 --- a/OSBindings/Mac/Clock SignalTests/m68kDecoderTests.mm +++ b/OSBindings/Mac/Clock SignalTests/m68kDecoderTests.mm @@ -246,14 +246,16 @@ template NSString *operand(Preinstruction instruction, uint16_t opco case Operation::DIVU: instruction = @"DIVU"; break; case Operation::DIVS: instruction = @"DIVS"; break; + case Operation::RTE: instruction = @"RTE"; break; + case Operation::RTR: instruction = @"RTR"; break; + + case Operation::TRAP: instruction = @"TRAP"; break; + case Operation::TRAPV: instruction = @"TRAPV"; break; + case Operation::CHK: instruction = @"CHK"; break; + /* TODO: - RTE, RTR, - - TRAP, TRAPV, - CHK, - EXG, SWAP, TAS,