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Corrects memptr leakage via BIT, and ld (de/bc/nn), A behaviour.
This commit is contained in:
Thomas Harte
parent
03501df9e5
commit
f0f9d5a6af
@ -23,6 +23,16 @@ class Z80MemptrTests: XCTestCase {
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return machine.value(for: .memPtr)
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}
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fileprivate func insert16(program: inout [UInt8], address: Int, offset: size_t) {
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program[offset] = UInt8(address & 0x00ff)
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program[offset + 1] = UInt8(address >> 8)
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}
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/*
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Re: comments below:
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All the CPU chips tested give the same results except KP1858BM1 and T34BM1 slices noted as "BM1".
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*/
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// LD A, (addr)
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func testLDAnn() {
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// MEMPTR = addr+1
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@ -39,11 +49,40 @@ class Z80MemptrTests: XCTestCase {
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}
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}
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/* TODO:
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LD (addr),A
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MEMPTR_low = (addr + 1) & #FF, MEMPTR_hi = A
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Note for *BM1: MEMPTR_low = (addr + 1) & #FF, MEMPTR_hi = 0
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*/
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// LD (bc/de),A, and LD (nn),A
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func testLDrpA() {
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// MEMPTR_low = (addr + 1) & #FF, MEMPTR_hi = A
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// Note for *BM1: MEMPTR_low = (addr + 1) & #FF, MEMPTR_hi = 0
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let bcProgram: [UInt8] = [
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0x02
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]
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let deProgram: [UInt8] = [
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0x12
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]
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var nnProgram: [UInt8] = [
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0x32, 0x00, 0x00
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]
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for addr in 0 ..< 256 {
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machine.setValue(UInt16(addr), for: .BC)
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machine.setValue(UInt16(addr), for: .DE)
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insert16(program: &nnProgram, address: addr, offset: 1)
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for a in 0 ..< 256 {
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machine.setValue(UInt16(a), for: .A)
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let expectedResult = UInt16(((addr + 1) & 0xff) + (a << 8))
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let bcResult = test(program: bcProgram, length: 7, initialValue: 0xffff)
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let deResult = test(program: deProgram, length: 7, initialValue: 0xffff)
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let nnResult = test(program: nnProgram, length: 13, initialValue: 0xffff)
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XCTAssertEqual(bcResult, expectedResult)
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XCTAssertEqual(deResult, expectedResult)
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XCTAssertEqual(nnResult, expectedResult)
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}
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}
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}
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// LD A, (rp)
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func testLDArp() {
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@ -68,19 +107,44 @@ class Z80MemptrTests: XCTestCase {
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}
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}
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/* TODO:
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LD (rp),A where rp -- BC or DE
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MEMPTR_low = (rp + 1) & #FF, MEMPTR_hi = A
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Note for *BM1: MEMPTR_low = (rp + 1) & #FF, MEMPTR_hi = 0
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*/
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// LD (addr), rp
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func testLDnnrp() {
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// MEMPTR = addr + 1
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var ldnnhlBaseProgram: [UInt8] = [
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0x22, 0x00, 0x00
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]
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var ldnnbcEDProgram: [UInt8] = [
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0xed, 0x43, 0x00, 0x00
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]
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var ldnndeEDProgram: [UInt8] = [
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0xed, 0x53, 0x00, 0x00
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]
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var ldnnhlEDProgram: [UInt8] = [
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0xed, 0x63, 0x00, 0x00
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]
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var ldnnspEDProgram: [UInt8] = [
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0xed, 0x73, 0x00, 0x00
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]
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/* TODO:
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LD (addr), rp
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MEMPTR = addr + 1
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*/
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for addr in 0 ..< 65536 {
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insert16(program: &ldnnhlBaseProgram, address: addr, offset: 1)
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insert16(program: &ldnnbcEDProgram, address: addr, offset: 2)
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insert16(program: &ldnndeEDProgram, address: addr, offset: 2)
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insert16(program: &ldnnhlEDProgram, address: addr, offset: 2)
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insert16(program: &ldnnspEDProgram, address: addr, offset: 2)
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let expectedResult = UInt16((addr + 1) & 0xffff)
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XCTAssertEqual(test(program: ldnnhlBaseProgram, length: 16, initialValue: expectedResult ^ 1), expectedResult)
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XCTAssertEqual(test(program: ldnnbcEDProgram, length: 20, initialValue: expectedResult ^ 1), expectedResult)
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XCTAssertEqual(test(program: ldnndeEDProgram, length: 20, initialValue: expectedResult ^ 1), expectedResult)
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XCTAssertEqual(test(program: ldnnhlEDProgram, length: 20, initialValue: expectedResult ^ 1), expectedResult)
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XCTAssertEqual(test(program: ldnnspEDProgram, length: 20, initialValue: expectedResult ^ 1), expectedResult)
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}
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}
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// LD rp, (addr)
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func testLDnnrp() {
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func testLDrpnn() {
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// MEMPTR = addr+1
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var hlBaseProgram: [UInt8] = [
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0x22, 0x00, 0x00
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@ -621,7 +621,7 @@ template < class T,
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case MicroOp::BIT: {
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uint8_t result = *static_cast<uint8_t *>(operation->source) & (1 << ((operation_ >> 3)&7));
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if(current_instruction_page_->is_indexed || ((operation_&0x08) == 7)) {
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if(current_instruction_page_->is_indexed || ((operation_&0x07) == 6)) {
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bit53_result_ = memptr_.bytes.high;
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} else {
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bit53_result_ = *static_cast<uint8_t *>(operation->source);
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@ -848,6 +848,10 @@ template < class T,
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memptr_.full = static_cast<uint16_t>(*static_cast<uint16_t *>(operation->source) + (int8_t)temp8_);
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break;
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case MicroOp::SetAddrAMemptr:
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memptr_.full = static_cast<uint16_t>(((*static_cast<uint16_t *>(operation->source) + 1)&0xff) + (a_ << 8));
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break;
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case MicroOp::IndexedPlaceHolder:
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return;
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}
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@ -351,7 +351,7 @@ void ProcessorStorage::assemble_base_page(InstructionPage &target, RegisterPair
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InstructionTable base_program_table = {
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/* 0x00 NOP */ NOP, /* 0x01 LD BC, nn */ StdInstr(Read16Inc(pc_, bc_)),
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/* 0x02 LD (BC), A */ StdInstr({MicroOp::Move16, &bc_.full, &memptr_.full}, Write3(memptr_, a_)),
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/* 0x02 LD (BC), A */ StdInstr({MicroOp::SetAddrAMemptr, &bc_.full}, Write3(bc_, a_)),
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/* 0x03 INC BC; 0x04 INC B; 0x05 DEC B; 0x06 LD B, n */
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INC_INC_DEC_LD(bc_, bc_.bytes.high),
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@ -366,7 +366,7 @@ void ProcessorStorage::assemble_base_page(InstructionPage &target, RegisterPair
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/* 0x0f RRCA */ StdInstr({MicroOp::RRCA}),
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/* 0x10 DJNZ */ Instr(6, ReadInc(pc_, temp8_), {MicroOp::DJNZ}, InternalOperation(10), {MicroOp::CalculateIndexAddress, &pc_.full}, {MicroOp::Move16, &memptr_.full, &pc_.full}),
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/* 0x11 LD DE, nn */ StdInstr(Read16Inc(pc_, de_)),
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/* 0x12 LD (DE), A */ StdInstr({MicroOp::Move16, &de_.full, &memptr_.full}, Write3(memptr_, a_)),
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/* 0x12 LD (DE), A */ StdInstr({MicroOp::SetAddrAMemptr, &de_.full}, Write3(de_, a_)),
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/* 0x13 INC DE; 0x14 INC D; 0x15 DEC D; 0x16 LD D, n */
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INC_INC_DEC_LD(de_, de_.bytes.high),
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@ -395,7 +395,7 @@ void ProcessorStorage::assemble_base_page(InstructionPage &target, RegisterPair
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/* 0x2f CPL */ StdInstr({MicroOp::CPL}),
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/* 0x30 JR NC */ JR(TestNC), /* 0x31 LD SP, nn */ StdInstr(Read16Inc(pc_, sp_)),
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/* 0x32 LD (nn), A */ StdInstr(Read16Inc(pc_, temp16_), Write3(temp16_, a_)),
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/* 0x32 LD (nn), A */ StdInstr(Read16Inc(pc_, temp16_), {MicroOp::SetAddrAMemptr, &temp16_.full}, Write3(temp16_, a_)),
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/* 0x33 INC SP */ Instr(8, {MicroOp::Increment16, &sp_.full}),
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/* 0x34 INC (HL) */ StdInstr(INDEX(), Read4(INDEX_ADDR(), temp8_), {MicroOp::Increment8, &temp8_}, Write3(INDEX_ADDR(), temp8_)),
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/* 0x35 DEC (HL) */ StdInstr(INDEX(), Read4(INDEX_ADDR(), temp8_), {MicroOp::Decrement8, &temp8_}, Write3(INDEX_ADDR(), temp8_)),
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@ -91,6 +91,8 @@ class ProcessorStorage {
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IndexedPlaceHolder,
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SetAddrAMemptr,
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Reset
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};
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Type type;
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