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Switch register-setting interface.

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This commit is contained in:
Thomas Harte 2022-05-26 07:52:14 -04:00
parent 866787c5d3
commit f3c0c62c79
8 changed files with 1096 additions and 1293 deletions
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600
OSBindings/Mac/Clock SignalTests/68000ArithmeticTests.mm
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117
OSBindings/Mac/Clock SignalTests/68000BCDTests.mm
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@ -32,13 +32,13 @@
_machine->set_program({ _machine->set_program({
0xc302, // ABCD D2, D1 0xc302, // ABCD D2, D1
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers){
state.registers.data[1] = 0x1234567a; registers.data[1] = 0x1234567a;
state.registers.data[2] = 0xf745ff78; registers.data[2] = 0xf745ff78;
_machine->set_processor_state(state); });
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssert(state.registers.status & ConditionCode::Carry); XCTAssert(state.registers.status & ConditionCode::Carry);
XCTAssertEqual(state.registers.data[1], 0x12345658); XCTAssertEqual(state.registers.data[1], 0x12345658);
XCTAssertEqual(state.registers.data[2], 0xf745ff78); XCTAssertEqual(state.registers.data[2], 0xf745ff78);
@ -48,14 +48,14 @@
_machine->set_program({ _machine->set_program({
0xc302, // ABCD D2, D1 0xc302, // ABCD D2, D1
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers){
state.registers.data[1] = 0x12345600; registers.data[1] = 0x12345600;
state.registers.data[2] = 0x12345600; registers.data[2] = 0x12345600;
state.registers.status = ConditionCode::Zero; registers.status = ConditionCode::Zero;
_machine->set_processor_state(state); });
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssert(state.registers.status & ConditionCode::Zero); XCTAssert(state.registers.status & ConditionCode::Zero);
XCTAssertEqual(state.registers.data[1], 0x12345600); XCTAssertEqual(state.registers.data[1], 0x12345600);
XCTAssertEqual(state.registers.data[2], 0x12345600); XCTAssertEqual(state.registers.data[2], 0x12345600);
@ -65,14 +65,14 @@
_machine->set_program({ _machine->set_program({
0xc302, // ABCD D2, D1 0xc302, // ABCD D2, D1
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers){
state.registers.data[1] = 0x12345645; registers.data[1] = 0x12345645;
state.registers.data[2] = 0x12345654; registers.data[2] = 0x12345654;
state.registers.status = ConditionCode::Zero; registers.status = ConditionCode::Zero;
_machine->set_processor_state(state); });
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssert(state.registers.status & ConditionCode::Negative); XCTAssert(state.registers.status & ConditionCode::Negative);
XCTAssertEqual(state.registers.data[1], 0x12345699); XCTAssertEqual(state.registers.data[1], 0x12345699);
XCTAssertEqual(state.registers.data[2], 0x12345654); XCTAssertEqual(state.registers.data[2], 0x12345654);
@ -82,14 +82,14 @@
_machine->set_program({ _machine->set_program({
0xc302, // ABCD D2, D1 0xc302, // ABCD D2, D1
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers){
state.registers.data[1] = 0x12345645; registers.data[1] = 0x12345645;
state.registers.data[2] = 0x12345654; registers.data[2] = 0x12345654;
state.registers.status = ConditionCode::Extend; registers.status = ConditionCode::Extend;
_machine->set_processor_state(state); });
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssert(state.registers.status & ConditionCode::Carry); XCTAssert(state.registers.status & ConditionCode::Carry);
XCTAssertEqual(state.registers.data[1], 0x12345600); XCTAssertEqual(state.registers.data[1], 0x12345600);
XCTAssertEqual(state.registers.data[2], 0x12345654); XCTAssertEqual(state.registers.data[2], 0x12345654);
@ -99,14 +99,14 @@
_machine->set_program({ _machine->set_program({
0xc302, // ABCD D2, D1 0xc302, // ABCD D2, D1
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers){
state.registers.data[1] = 0x1234563e; registers.data[1] = 0x1234563e;
state.registers.data[2] = 0x1234563e; registers.data[2] = 0x1234563e;
state.registers.status = ConditionCode::Extend; registers.status = ConditionCode::Extend;
_machine->set_processor_state(state); });
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssert(state.registers.status & ConditionCode::Overflow); XCTAssert(state.registers.status & ConditionCode::Overflow);
XCTAssertEqual(state.registers.data[1], 0x12345683); XCTAssertEqual(state.registers.data[1], 0x12345683);
XCTAssertEqual(state.registers.data[2], 0x1234563e); XCTAssertEqual(state.registers.data[2], 0x1234563e);
@ -116,17 +116,16 @@
_machine->set_program({ _machine->set_program({
0xc30a, // ABCD -(A2), -(A1) 0xc30a, // ABCD -(A2), -(A1)
}); });
_machine->set_registers([=](auto &registers){
registers.address[1] = 0x3001;
registers.address[2] = 0x4001;
registers.status = ConditionCode::Extend;
});
*_machine->ram_at(0x3000) = 0xa200; *_machine->ram_at(0x3000) = 0xa200;
*_machine->ram_at(0x4000) = 0x1900; *_machine->ram_at(0x4000) = 0x1900;
auto state = _machine->get_processor_state();
state.registers.address[1] = 0x3001;
state.registers.address[2] = 0x4001;
state.registers.status = ConditionCode::Extend;
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssert(state.registers.status & ConditionCode::Carry); XCTAssert(state.registers.status & ConditionCode::Carry);
XCTAssert(state.registers.status & ConditionCode::Extend); XCTAssert(state.registers.status & ConditionCode::Extend);
XCTAssertEqual(state.registers.address[1], 0x3000); XCTAssertEqual(state.registers.address[1], 0x3000);
@ -139,15 +138,14 @@
_machine->set_program({ _machine->set_program({
0xc309, // ABCD -(A1), -(A1) 0xc309, // ABCD -(A1), -(A1)
}); });
_machine->set_registers([=](auto &registers){
registers.address[1] = 0x3002;
registers.status = ConditionCode::Extend;
});
*_machine->ram_at(0x3000) = 0x19a2; *_machine->ram_at(0x3000) = 0x19a2;
auto state = _machine->get_processor_state();
state.registers.address[1] = 0x3002;
state.registers.status = ConditionCode::Extend;
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssert(state.registers.status & ConditionCode::Carry); XCTAssert(state.registers.status & ConditionCode::Carry);
XCTAssert(state.registers.status & ConditionCode::Extend); XCTAssert(state.registers.status & ConditionCode::Extend);
XCTAssertEqual(state.registers.address[1], 0x3000); XCTAssertEqual(state.registers.address[1], 0x3000);
@ -160,11 +158,10 @@
_machine->set_program({ _machine->set_program({
0x4801 // NBCD D1 0x4801 // NBCD D1
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers){
state.registers.status |= ccr; registers.status |= ccr;
state.registers.data[1] = d1; registers.data[1] = d1;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
XCTAssertEqual(6, _machine->get_cycle_count()); XCTAssertEqual(6, _machine->get_cycle_count());
@ -222,15 +219,14 @@
_machine->set_program({ _machine->set_program({
0x8302 // SBCD D2, D1 0x8302 // SBCD D2, D1
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers){
state.registers.status |= ccr; registers.status |= ccr;
state.registers.data[1] = d1; registers.data[1] = d1;
state.registers.data[2] = d2; registers.data[2] = d2;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(6, _machine->get_cycle_count()); XCTAssertEqual(6, _machine->get_cycle_count());
XCTAssertEqual(state.registers.data[2], d2); XCTAssertEqual(state.registers.data[2], d2);
} }
@ -273,15 +269,14 @@
}); });
*_machine->ram_at(0x3000) = 0xa200; *_machine->ram_at(0x3000) = 0xa200;
*_machine->ram_at(0x4000) = 0x1900; *_machine->ram_at(0x4000) = 0x1900;
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers){
state.registers.address[1] = 0x3001; registers.address[1] = 0x3001;
state.registers.address[2] = 0x4001; registers.address[2] = 0x4001;
state.registers.status |= ConditionCode::Extend; registers.status |= ConditionCode::Extend;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(18, _machine->get_cycle_count()); XCTAssertEqual(18, _machine->get_cycle_count());
XCTAssertEqual(*_machine->ram_at(0x3000), 0x8200); XCTAssertEqual(*_machine->ram_at(0x3000), 0x8200);
XCTAssertEqual(*_machine->ram_at(0x4000), 0x1900); XCTAssertEqual(*_machine->ram_at(0x4000), 0x1900);

540
OSBindings/Mac/Clock SignalTests/68000BitwiseTests.mm
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56
OSBindings/Mac/Clock SignalTests/68000ControlFlowTests.mm
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@ -145,15 +145,14 @@
_machine->set_program({ _machine->set_program({
0x4581 // CHK D1, D2 0x4581 // CHK D1, D2
}, 0); }, 0);
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[1] = d1; registers.data[1] = d1;
state.registers.data[2] = d2; registers.data[2] = d2;
state.registers.status |= ConditionCode::AllConditions; registers.status |= ConditionCode::AllConditions;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[1], d1); XCTAssertEqual(state.registers.data[1], d1);
XCTAssertEqual(state.registers.data[2], d2); XCTAssertEqual(state.registers.data[2], d2);
} }
@ -201,14 +200,13 @@
_machine->set_program({ _machine->set_program({
opcode, 0x0008 // DBcc D2, +8 opcode, 0x0008 // DBcc D2, +8
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.status = status; registers.status = status;
state.registers.data[2] = 1; registers.data[2] = 1;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[2], d2Output); XCTAssertEqual(state.registers.data[2], d2Output);
XCTAssertEqual(state.registers.status, status); XCTAssertEqual(state.registers.status, status);
} }
@ -382,13 +380,12 @@
0x4ed1 // JMP (A1) 0x4ed1 // JMP (A1)
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.address[1] = 0x3000; registers.address[1] = 0x3000;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.address[1], 0x3000); XCTAssertEqual(state.registers.address[1], 0x3000);
XCTAssertEqual(state.registers.program_counter, 0x3000 + 4); XCTAssertEqual(state.registers.program_counter, 0x3000 + 4);
XCTAssertEqual(8, _machine->get_cycle_count()); XCTAssertEqual(8, _machine->get_cycle_count());
@ -490,17 +487,16 @@
_machine->set_program({ _machine->set_program({
0x4e41 // TRAP #1 0x4e41 // TRAP #1
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.status = 0x700; registers.status = 0x700;
state.registers.user_stack_pointer = 0x200; registers.user_stack_pointer = 0x200;
state.registers.supervisor_stack_pointer = 0x206; registers.supervisor_stack_pointer = 0x206;
});
*_machine->ram_at(0x84) = 0xfffe; *_machine->ram_at(0x84) = 0xfffe;
*_machine->ram_at(0xfffe) = 0x4e71; *_machine->ram_at(0xfffe) = 0x4e71;
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.status, 0x2700); XCTAssertEqual(state.registers.status, 0x2700);
XCTAssertEqual(*_machine->ram_at(0x200), 0x700); XCTAssertEqual(*_machine->ram_at(0x200), 0x700);
XCTAssertEqual(*_machine->ram_at(0x202), 0x0000); XCTAssertEqual(*_machine->ram_at(0x202), 0x0000);
@ -516,16 +512,16 @@
0x4e76 // TRAPV 0x4e76 // TRAPV
}, 0x206); }, 0x206);
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.status = 0x702; registers.status = 0x702;
state.registers.supervisor_stack_pointer = 0x206; registers.supervisor_stack_pointer = 0x206;
});
*_machine->ram_at(0x1e) = 0xfffe; *_machine->ram_at(0x1e) = 0xfffe;
*_machine->ram_at(0xfffe) = 0x4e71; *_machine->ram_at(0xfffe) = 0x4e71;
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.status, 0x2702); XCTAssertEqual(state.registers.status, 0x2702);
XCTAssertEqual(state.registers.stack_pointer(), 0x200); XCTAssertEqual(state.registers.stack_pointer(), 0x200);
XCTAssertEqual(*_machine->ram_at(0x202), 0x0000); XCTAssertEqual(*_machine->ram_at(0x202), 0x0000);

550
OSBindings/Mac/Clock SignalTests/68000MoveTests.mm
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489
OSBindings/Mac/Clock SignalTests/68000RollShiftTests.mm
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@ -33,14 +33,13 @@
_machine->set_program({ _machine->set_program({
0xe521 // ASL.B D2, D1 0xe521 // ASL.B D2, D1
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[1] = 0xce3dd567; registers.data[1] = 0xce3dd567;
state.registers.data[2] = 2; registers.data[2] = 2;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[1], 0xce3dd59c); XCTAssertEqual(state.registers.data[1], 0xce3dd59c);
XCTAssertEqual(state.registers.data[2], 2); XCTAssertEqual(state.registers.data[2], 2);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative | ConditionCode::Overflow | ConditionCode::Carry); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative | ConditionCode::Overflow | ConditionCode::Carry);
@ -51,14 +50,13 @@
_machine->set_program({ _machine->set_program({
0xe521 // ASL.B D2, D1 0xe521 // ASL.B D2, D1
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[1] = 0xce3dd567; registers.data[1] = 0xce3dd567;
state.registers.data[2] = 105; registers.data[2] = 105;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[1], 0xce3dd500); XCTAssertEqual(state.registers.data[1], 0xce3dd500);
XCTAssertEqual(state.registers.data[2], 105); XCTAssertEqual(state.registers.data[2], 105);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Overflow | ConditionCode::Zero); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Overflow | ConditionCode::Zero);
@ -69,14 +67,13 @@
_machine->set_program({ _machine->set_program({
0xe561 // ASL.w D2, D1 0xe561 // ASL.w D2, D1
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[1] = 0xce3dd567; registers.data[1] = 0xce3dd567;
state.registers.data[2] = 0; registers.data[2] = 0;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[1], 0xce3dd567); XCTAssertEqual(state.registers.data[1], 0xce3dd567);
XCTAssertEqual(state.registers.data[2], 0); XCTAssertEqual(state.registers.data[2], 0);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
@ -87,14 +84,13 @@
_machine->set_program({ _machine->set_program({
0xe561 // ASL.w D2, D1 0xe561 // ASL.w D2, D1
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[1] = 0xce3dd567; registers.data[1] = 0xce3dd567;
state.registers.data[2] = 0xb; registers.data[2] = 0xb;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[1], 0xce3d3800); XCTAssertEqual(state.registers.data[1], 0xce3d3800);
XCTAssertEqual(state.registers.data[2], 0xb); XCTAssertEqual(state.registers.data[2], 0xb);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Overflow | ConditionCode::Carry); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Overflow | ConditionCode::Carry);
@ -105,14 +101,13 @@
_machine->set_program({ _machine->set_program({
0xe5a1 // ASL.l D2, D1 0xe5a1 // ASL.l D2, D1
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[1] = 0xce3dd567; registers.data[1] = 0xce3dd567;
state.registers.data[2] = 0x20; registers.data[2] = 0x20;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[1], 0); XCTAssertEqual(state.registers.data[1], 0);
XCTAssertEqual(state.registers.data[2], 0x20); XCTAssertEqual(state.registers.data[2], 0x20);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Overflow | ConditionCode::Carry | ConditionCode::Zero); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Overflow | ConditionCode::Carry | ConditionCode::Zero);
@ -123,14 +118,13 @@
_machine->set_program({ _machine->set_program({
0xe181 // ASL.l #8, D1 0xe181 // ASL.l #8, D1
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[1] = 0xce3dd567; registers.data[1] = 0xce3dd567;
state.registers.data[2] = 0x20; registers.data[2] = 0x20;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[1], 0x3dd56700); XCTAssertEqual(state.registers.data[1], 0x3dd56700);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Overflow); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Overflow);
XCTAssertEqual(24, _machine->get_cycle_count()); XCTAssertEqual(24, _machine->get_cycle_count());
@ -172,14 +166,13 @@
_machine->set_program({ _machine->set_program({
0xe421 // ASR.B D2, D1 0xe421 // ASR.B D2, D1
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[1] = 0xce3dd567; registers.data[1] = 0xce3dd567;
state.registers.data[2] = 2; registers.data[2] = 2;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[1], 0xce3dd519); XCTAssertEqual(state.registers.data[1], 0xce3dd519);
XCTAssertEqual(state.registers.data[2], 2); XCTAssertEqual(state.registers.data[2], 2);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry);
@ -190,14 +183,13 @@
_machine->set_program({ _machine->set_program({
0xe421 // ASR.B D2, D1 0xe421 // ASR.B D2, D1
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[1] = 0xce3dd567; registers.data[1] = 0xce3dd567;
state.registers.data[2] = 105; registers.data[2] = 105;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[1], 0xce3dd500); XCTAssertEqual(state.registers.data[1], 0xce3dd500);
XCTAssertEqual(state.registers.data[2], 105); XCTAssertEqual(state.registers.data[2], 105);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
@ -208,14 +200,13 @@
_machine->set_program({ _machine->set_program({
0xe461 // ASR.w D2, D1 0xe461 // ASR.w D2, D1
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[1] = 0xce3dd567; registers.data[1] = 0xce3dd567;
state.registers.data[2] = 0; registers.data[2] = 0;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[1], 0xce3dd567); XCTAssertEqual(state.registers.data[1], 0xce3dd567);
XCTAssertEqual(state.registers.data[2], 0); XCTAssertEqual(state.registers.data[2], 0);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
@ -226,14 +217,13 @@
_machine->set_program({ _machine->set_program({
0xe461 // ASR.w D2, D1 0xe461 // ASR.w D2, D1
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[1] = 0xce3dd567; registers.data[1] = 0xce3dd567;
state.registers.data[2] = 0xb; registers.data[2] = 0xb;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[1], 0xce3dfffa); XCTAssertEqual(state.registers.data[1], 0xce3dfffa);
XCTAssertEqual(state.registers.data[2], 0xb); XCTAssertEqual(state.registers.data[2], 0xb);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative | ConditionCode::Carry); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative | ConditionCode::Carry);
@ -244,14 +234,13 @@
_machine->set_program({ _machine->set_program({
0xe4a1 // ASR.l D2, D1 0xe4a1 // ASR.l D2, D1
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[1] = 0xce3dd567; registers.data[1] = 0xce3dd567;
state.registers.data[2] = 0x20; registers.data[2] = 0x20;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[1], 0xffffffff); XCTAssertEqual(state.registers.data[1], 0xffffffff);
XCTAssertEqual(state.registers.data[2], 0x20); XCTAssertEqual(state.registers.data[2], 0x20);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative | ConditionCode::Carry); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative | ConditionCode::Carry);
@ -262,14 +251,13 @@
_machine->set_program({ _machine->set_program({
0xe081 // ASR.l #8, D1 0xe081 // ASR.l #8, D1
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[1] = 0xce3dd567; registers.data[1] = 0xce3dd567;
state.registers.data[2] = 0x20; registers.data[2] = 0x20;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[1], 0xffce3dd5); XCTAssertEqual(state.registers.data[1], 0xffce3dd5);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
XCTAssertEqual(24, _machine->get_cycle_count()); XCTAssertEqual(24, _machine->get_cycle_count());
@ -311,14 +299,13 @@
_machine->set_program({ _machine->set_program({
0xe529 // LSL.b D2, D1 0xe529 // LSL.b D2, D1
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[1] = 0xce3dd567; registers.data[1] = 0xce3dd567;
state.registers.data[2] = 2; registers.data[2] = 2;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[1], 0xce3dd59c); XCTAssertEqual(state.registers.data[1], 0xce3dd59c);
XCTAssertEqual(state.registers.data[2], 2); XCTAssertEqual(state.registers.data[2], 2);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative | ConditionCode::Carry); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative | ConditionCode::Carry);
@ -329,14 +316,13 @@
_machine->set_program({ _machine->set_program({
0xe529 // LSL.b D2, D1 0xe529 // LSL.b D2, D1
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[1] = 0xce3dd567; registers.data[1] = 0xce3dd567;
state.registers.data[2] = 0x69; registers.data[2] = 0x69;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[1], 0xce3dd500); XCTAssertEqual(state.registers.data[1], 0xce3dd500);
XCTAssertEqual(state.registers.data[2], 0x69); XCTAssertEqual(state.registers.data[2], 0x69);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
@ -347,14 +333,13 @@
_machine->set_program({ _machine->set_program({
0xe569 // LSL.w D2, D1 0xe569 // LSL.w D2, D1
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[1] = 0xce3dd567; registers.data[1] = 0xce3dd567;
state.registers.data[2] = 0; registers.data[2] = 0;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[1], 0xce3dd567); XCTAssertEqual(state.registers.data[1], 0xce3dd567);
XCTAssertEqual(state.registers.data[2], 0); XCTAssertEqual(state.registers.data[2], 0);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
@ -365,14 +350,13 @@
_machine->set_program({ _machine->set_program({
0xe569 // LSL.w D2, D1 0xe569 // LSL.w D2, D1
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[1] = 0xce3dd567; registers.data[1] = 0xce3dd567;
state.registers.data[2] = 0xb; registers.data[2] = 0xb;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[1], 0xce3d3800); XCTAssertEqual(state.registers.data[1], 0xce3d3800);
XCTAssertEqual(state.registers.data[2], 0xb); XCTAssertEqual(state.registers.data[2], 0xb);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry);
@ -383,14 +367,13 @@
_machine->set_program({ _machine->set_program({
0xe5a9 // LSL.l D2, D1 0xe5a9 // LSL.l D2, D1
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[1] = 0xce3dd567; registers.data[1] = 0xce3dd567;
state.registers.data[2] = 0x20; registers.data[2] = 0x20;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[1], 0); XCTAssertEqual(state.registers.data[1], 0);
XCTAssertEqual(state.registers.data[2], 0x20); XCTAssertEqual(state.registers.data[2], 0x20);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Zero); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Zero);
@ -401,13 +384,12 @@
_machine->set_program({ _machine->set_program({
0xe189 // LSL.l #8, D1 0xe189 // LSL.l #8, D1
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[1] = 0xce3dd567; registers.data[1] = 0xce3dd567;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[1], 0x3dd56700); XCTAssertEqual(state.registers.data[1], 0x3dd56700);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
XCTAssertEqual(24, _machine->get_cycle_count()); XCTAssertEqual(24, _machine->get_cycle_count());
@ -433,14 +415,13 @@
_machine->set_program({ _machine->set_program({
0xe429 // LSR.b D2, D1 0xe429 // LSR.b D2, D1
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[1] = 0xce3dd567; registers.data[1] = 0xce3dd567;
state.registers.data[2] = 2; registers.data[2] = 2;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[1], 0xce3dd519); XCTAssertEqual(state.registers.data[1], 0xce3dd519);
XCTAssertEqual(state.registers.data[2], 2); XCTAssertEqual(state.registers.data[2], 2);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry);
@ -451,14 +432,13 @@
_machine->set_program({ _machine->set_program({
0xe429 // LSR.b D2, D1 0xe429 // LSR.b D2, D1
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[1] = 0xce3dd567; registers.data[1] = 0xce3dd567;
state.registers.data[2] = 0x69; registers.data[2] = 0x69;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[1], 0xce3dd500); XCTAssertEqual(state.registers.data[1], 0xce3dd500);
XCTAssertEqual(state.registers.data[2], 0x69); XCTAssertEqual(state.registers.data[2], 0x69);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
@ -469,14 +449,13 @@
_machine->set_program({ _machine->set_program({
0xe469 // LSR.w D2, D1 0xe469 // LSR.w D2, D1
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[1] = 0xce3dd567; registers.data[1] = 0xce3dd567;
state.registers.data[2] = 0; registers.data[2] = 0;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[1], 0xce3dd567); XCTAssertEqual(state.registers.data[1], 0xce3dd567);
XCTAssertEqual(state.registers.data[2], 0); XCTAssertEqual(state.registers.data[2], 0);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
@ -487,14 +466,13 @@
_machine->set_program({ _machine->set_program({
0xe469 // LSR.w D2, D1 0xe469 // LSR.w D2, D1
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[1] = 0xce3dd567; registers.data[1] = 0xce3dd567;
state.registers.data[2] = 0xb; registers.data[2] = 0xb;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[1], 0xce3d001a); XCTAssertEqual(state.registers.data[1], 0xce3d001a);
XCTAssertEqual(state.registers.data[2], 0xb); XCTAssertEqual(state.registers.data[2], 0xb);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry);
@ -505,14 +483,13 @@
_machine->set_program({ _machine->set_program({
0xe4a9 // LSR.l D2, D1 0xe4a9 // LSR.l D2, D1
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[1] = 0xce3dd567; registers.data[1] = 0xce3dd567;
state.registers.data[2] = 0x20; registers.data[2] = 0x20;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[1], 0); XCTAssertEqual(state.registers.data[1], 0);
XCTAssertEqual(state.registers.data[2], 0x20); XCTAssertEqual(state.registers.data[2], 0x20);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Zero); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Zero);
@ -523,13 +500,12 @@
_machine->set_program({ _machine->set_program({
0xe089 // LSR.L #8, D1 0xe089 // LSR.L #8, D1
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[1] = 0xce3dd567; registers.data[1] = 0xce3dd567;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[1], 0xce3dd5); XCTAssertEqual(state.registers.data[1], 0xce3dd5);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
XCTAssertEqual(24, _machine->get_cycle_count()); XCTAssertEqual(24, _machine->get_cycle_count());
@ -555,13 +531,12 @@
_machine->set_program({ _machine->set_program({
0xe118 // ROL.B #8, D0 0xe118 // ROL.B #8, D0
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[0] = 0xce3dd567; registers.data[0] = 0xce3dd567;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[0], 0xce3dd567); XCTAssertEqual(state.registers.data[0], 0xce3dd567);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry);
XCTAssertEqual(22, _machine->get_cycle_count()); XCTAssertEqual(22, _machine->get_cycle_count());
@ -571,13 +546,12 @@
_machine->set_program({ _machine->set_program({
0xe318 // ROL.B #1, D0 0xe318 // ROL.B #1, D0
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[0] = 0xce3dd567; registers.data[0] = 0xce3dd567;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[0], 0xce3dd5ce); XCTAssertEqual(state.registers.data[0], 0xce3dd5ce);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
XCTAssertEqual(8, _machine->get_cycle_count()); XCTAssertEqual(8, _machine->get_cycle_count());
@ -587,14 +561,13 @@
_machine->set_program({ _machine->set_program({
0xe518 // ROL.B #2, D0 0xe518 // ROL.B #2, D0
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[0] = 0xce3dd567; registers.data[0] = 0xce3dd567;
state.registers.status = ConditionCode::AllConditions; registers.status = ConditionCode::AllConditions;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[0], 0xce3dd59d); XCTAssertEqual(state.registers.data[0], 0xce3dd59d);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative | ConditionCode::Extend | ConditionCode::Carry); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative | ConditionCode::Extend | ConditionCode::Carry);
XCTAssertEqual(10, _machine->get_cycle_count()); XCTAssertEqual(10, _machine->get_cycle_count());
@ -604,14 +577,13 @@
_machine->set_program({ _machine->set_program({
0xef18 // ROL.B #7, D0 0xef18 // ROL.B #7, D0
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[0] = 0xce3dd567; registers.data[0] = 0xce3dd567;
state.registers.status = ConditionCode::AllConditions; registers.status = ConditionCode::AllConditions;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[0], 0xce3dd5b3); XCTAssertEqual(state.registers.data[0], 0xce3dd5b3);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative | ConditionCode::Extend | ConditionCode::Carry); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative | ConditionCode::Extend | ConditionCode::Carry);
XCTAssertEqual(20, _machine->get_cycle_count()); XCTAssertEqual(20, _machine->get_cycle_count());
@ -621,14 +593,13 @@
_machine->set_program({ _machine->set_program({
0xe158 // ROL.w #7, D0 0xe158 // ROL.w #7, D0
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[0] = 0xce3dd567; registers.data[0] = 0xce3dd567;
state.registers.status = ConditionCode::AllConditions; registers.status = ConditionCode::AllConditions;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[0], 0xce3d67d5); XCTAssertEqual(state.registers.data[0], 0xce3d67d5);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry);
XCTAssertEqual(22, _machine->get_cycle_count()); XCTAssertEqual(22, _machine->get_cycle_count());
@ -638,14 +609,13 @@
_machine->set_program({ _machine->set_program({
0xe798 // ROL.l #3, D0 0xe798 // ROL.l #3, D0
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[0] = 0xce3dd567; registers.data[0] = 0xce3dd567;
state.registers.status = ConditionCode::AllConditions; registers.status = ConditionCode::AllConditions;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[0], 0x71eeab3e); XCTAssertEqual(state.registers.data[0], 0x71eeab3e);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
XCTAssertEqual(14, _machine->get_cycle_count()); XCTAssertEqual(14, _machine->get_cycle_count());
@ -655,12 +625,11 @@
_machine->set_program({ _machine->set_program({
0xe378 // ROL.l D1, D0 0xe378 // ROL.l D1, D0
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[0] = 0xce3dd567; registers.data[0] = 0xce3dd567;
state.registers.data[1] = d1; registers.data[1] = d1;
state.registers.status = ConditionCode::AllConditions; registers.status = ConditionCode::AllConditions;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
} }
@ -695,15 +664,14 @@
_machine->set_program({ _machine->set_program({
0xe3b8 // ROL.l D1, D0 0xe3b8 // ROL.l D1, D0
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[0] = 0xce3dd567; registers.data[0] = 0xce3dd567;
state.registers.data[1] = 200; registers.data[1] = 200;
state.registers.status = ConditionCode::AllConditions; registers.status = ConditionCode::AllConditions;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[0], 0x3dd567ce); XCTAssertEqual(state.registers.data[0], 0x3dd567ce);
XCTAssertEqual(state.registers.data[1], 200); XCTAssertEqual(state.registers.data[1], 200);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
@ -744,10 +712,9 @@
_machine->set_program({ _machine->set_program({
uint16_t(0xe018 | (immediate << 9)) // ROR.b #, D0 uint16_t(0xe018 | (immediate << 9)) // ROR.b #, D0
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[0] = 0xce3dd599; registers.data[0] = 0xce3dd599;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
} }
@ -791,13 +758,12 @@
_machine->set_program({ _machine->set_program({
0xec58 // ROR.w #6, D0 0xec58 // ROR.w #6, D0
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[0] = 0xce3dd599; registers.data[0] = 0xce3dd599;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[0], 0xce3d6756); XCTAssertEqual(state.registers.data[0], 0xce3d6756);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
XCTAssertEqual(18, _machine->get_cycle_count()); XCTAssertEqual(18, _machine->get_cycle_count());
@ -807,13 +773,12 @@
_machine->set_program({ _machine->set_program({
0xea98 // ROR.l #5, D0 0xea98 // ROR.l #5, D0
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[0] = 0xce3dd599; registers.data[0] = 0xce3dd599;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[0], 0xce71eeac); XCTAssertEqual(state.registers.data[0], 0xce71eeac);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Negative); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Negative);
XCTAssertEqual(18, _machine->get_cycle_count()); XCTAssertEqual(18, _machine->get_cycle_count());
@ -823,14 +788,13 @@
_machine->set_program({ _machine->set_program({
0xe238 // ROR.b D1, D0 0xe238 // ROR.b D1, D0
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[0] = 0xce3dd599; registers.data[0] = 0xce3dd599;
state.registers.data[1] = 20; registers.data[1] = 20;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[0], 0xce3dd599); XCTAssertEqual(state.registers.data[0], 0xce3dd599);
XCTAssertEqual(state.registers.data[1], 20); XCTAssertEqual(state.registers.data[1], 20);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Negative); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Negative);
@ -841,14 +805,13 @@
_machine->set_program({ _machine->set_program({
0xe2b8 // ROR.l D1, D0 0xe2b8 // ROR.l D1, D0
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[0] = 0xce3dd599; registers.data[0] = 0xce3dd599;
state.registers.data[1] = 26; registers.data[1] = 26;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[0], 0x8f756673); XCTAssertEqual(state.registers.data[0], 0x8f756673);
XCTAssertEqual(state.registers.data[1], 26); XCTAssertEqual(state.registers.data[1], 26);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Negative); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Negative);
@ -888,15 +851,14 @@
_machine->set_program({ _machine->set_program({
0xe330 // ROXL.b D1, D0 0xe330 // ROXL.b D1, D0
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[0] = 0xce3dd567; registers.data[0] = 0xce3dd567;
state.registers.data[1] = 9; registers.data[1] = 9;
state.registers.status |= ccr; registers.status |= ccr;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(24, _machine->get_cycle_count()); XCTAssertEqual(24, _machine->get_cycle_count());
XCTAssertEqual(state.registers.data[0], 0xce3dd567); XCTAssertEqual(state.registers.data[0], 0xce3dd567);
XCTAssertEqual(state.registers.data[1], 9); XCTAssertEqual(state.registers.data[1], 9);
@ -920,15 +882,14 @@
_machine->set_program({ _machine->set_program({
0xe370 // ROXL.w D1, D0 0xe370 // ROXL.w D1, D0
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[0] = 0xce3dd567; registers.data[0] = 0xce3dd567;
state.registers.data[1] = d1; registers.data[1] = d1;
state.registers.status |= ccr; registers.status |= ccr;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[1], d1); XCTAssertEqual(state.registers.data[1], d1);
} }
@ -963,15 +924,14 @@
_machine->set_program({ _machine->set_program({
0xe3b0 // ROXL.l D1, D0 0xe3b0 // ROXL.l D1, D0
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[0] = 0xce3dd567; registers.data[0] = 0xce3dd567;
state.registers.data[1] = 33; registers.data[1] = 33;
state.registers.status |= ConditionCode::Extend; registers.status |= ConditionCode::Extend;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[0], 0xce3dd567); XCTAssertEqual(state.registers.data[0], 0xce3dd567);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative | ConditionCode::Carry | ConditionCode::Extend); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative | ConditionCode::Carry | ConditionCode::Extend);
XCTAssertEqual(74, _machine->get_cycle_count()); XCTAssertEqual(74, _machine->get_cycle_count());
@ -981,14 +941,13 @@
_machine->set_program({ _machine->set_program({
0xe950 // ROXL.w #4, D0 0xe950 // ROXL.w #4, D0
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[0] = 0xce3d3600; registers.data[0] = 0xce3d3600;
state.registers.status |= ConditionCode::Extend; registers.status |= ConditionCode::Extend;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[0], 0xce3d6009); XCTAssertEqual(state.registers.data[0], 0xce3d6009);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry);
XCTAssertEqual(14, _machine->get_cycle_count()); XCTAssertEqual(14, _machine->get_cycle_count());
@ -1014,15 +973,14 @@
_machine->set_program({ _machine->set_program({
0xe230 // ROXR.b D1, D0 0xe230 // ROXR.b D1, D0
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[0] = 0xce3dd567; registers.data[0] = 0xce3dd567;
state.registers.data[1] = 9; registers.data[1] = 9;
state.registers.status |= ccr; registers.status |= ccr;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(24, _machine->get_cycle_count()); XCTAssertEqual(24, _machine->get_cycle_count());
XCTAssertEqual(state.registers.data[0], 0xce3dd567); XCTAssertEqual(state.registers.data[0], 0xce3dd567);
XCTAssertEqual(state.registers.data[1], 9); XCTAssertEqual(state.registers.data[1], 9);
@ -1046,15 +1004,14 @@
_machine->set_program({ _machine->set_program({
0xe270 // ROXR.w D1, D0 0xe270 // ROXR.w D1, D0
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[0] = 0xce3dd567; registers.data[0] = 0xce3dd567;
state.registers.data[1] = d1; registers.data[1] = d1;
state.registers.status |= ccr; registers.status |= ccr;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[1], d1); XCTAssertEqual(state.registers.data[1], d1);
} }
@ -1089,14 +1046,13 @@
_machine->set_program({ _machine->set_program({
0xe890 // ROXR.L #4, D0 0xe890 // ROXR.L #4, D0
}); });
auto state = _machine->get_processor_state(); _machine->set_registers([=](auto &registers) {
state.registers.data[0] = 0xce3d3600; registers.data[0] = 0xce3d3600;
state.registers.status |= ConditionCode::Extend; registers.status |= ConditionCode::Extend;
});
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(state.registers.data[0], 0x1ce3d360); XCTAssertEqual(state.registers.data[0], 0x1ce3d360);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
XCTAssertEqual(16, _machine->get_cycle_count()); XCTAssertEqual(16, _machine->get_cycle_count());
@ -1106,14 +1062,13 @@
_machine->set_program({ _machine->set_program({
0xe4f8, 0x3000 // ROXR.W ($3000).W 0xe4f8, 0x3000 // ROXR.W ($3000).W
}); });
_machine->set_registers([=](auto &registers) {
registers.status |= ConditionCode::Extend;
});
*_machine->ram_at(0x3000) = 0xd567; *_machine->ram_at(0x3000) = 0xd567;
auto state = _machine->get_processor_state();
state.registers.status |= ConditionCode::Extend;
_machine->set_processor_state(state);
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
XCTAssertEqual(*_machine->ram_at(0x3000), 0xeab3); XCTAssertEqual(*_machine->ram_at(0x3000), 0xeab3);
XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Extend | ConditionCode::Negative); XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Extend | ConditionCode::Negative);
XCTAssertEqual(16, _machine->get_cycle_count()); XCTAssertEqual(16, _machine->get_cycle_count());

10
OSBindings/Mac/Clock SignalTests/68000Tests.mm
View File

@ -125,15 +125,13 @@ class CPU::MC68000::ProcessorStorageTests {
_machine->set_program({ _machine->set_program({
0xc100 // ABCD D0, D0 0xc100 // ABCD D0, D0
}); });
auto state = _machine->get_processor_state();
const uint8_t bcd_d = ((d / 10) * 16) + (d % 10); const uint8_t bcd_d = ((d / 10) * 16) + (d % 10);
state.registers.data[0] = bcd_d; _machine->set_registers([=](auto &registers){
_machine->set_processor_state(state); registers.data[0] = bcd_d;
});
_machine->run_for_instructions(1); _machine->run_for_instructions(1);
state = _machine->get_processor_state(); const auto state = _machine->get_processor_state();
const uint8_t double_d = (d * 2) % 100; const uint8_t double_d = (d * 2) % 100;
const uint8_t bcd_double_d = ((double_d / 10) * 16) + (double_d % 10); const uint8_t bcd_double_d = ((double_d / 10) * 16) + (double_d % 10);
XCTAssert(state.registers.data[0] == bcd_double_d, "%02x + %02x = %02x; should equal %02x", bcd_d, bcd_d, state.registers.data[0], bcd_double_d); XCTAssert(state.registers.data[0] == bcd_double_d, "%02x + %02x = %02x; should equal %02x", bcd_d, bcd_d, state.registers.data[0], bcd_double_d);

27
OSBindings/Mac/Clock SignalTests/TestRunner68000.hpp
View File

@ -10,6 +10,7 @@
#define TestRunner68000_h #define TestRunner68000_h
#include <array> #include <array>
#include <functional>
#include <vector> #include <vector>
#include "../../../Processors/68000Mk2/68000Mk2.hpp" #include "../../../Processors/68000Mk2/68000Mk2.hpp"
@ -31,16 +32,24 @@ class RAM68000: public CPU::MC68000Mk2::BusHandler {
void set_program( void set_program(
const std::vector<uint16_t> &program, const std::vector<uint16_t> &program,
uint32_t stack_pointer = 0x206) { uint32_t stack_pointer = 0x206
) {
memcpy(&ram_[0x1000 >> 1], program.data(), program.size() * sizeof(uint16_t)); memcpy(&ram_[0x1000 >> 1], program.data(), program.size() * sizeof(uint16_t));
// Ensure the condition codes start unset and set the initial program counter // Ensure the condition codes start unset and set the initial program counter
// and supervisor stack pointer. // and supervisor stack pointer, as well as starting in supervisor mode.
auto state = get_processor_state(); set_registers([=](InstructionSet::M68k::RegisterSet &registers){
state.registers.status &= ~ConditionCode::AllConditions; registers.status &= ~ConditionCode::AllConditions;
state.registers.program_counter = initial_pc(); registers.status |= 0x2700;
state.registers.supervisor_stack_pointer = stack_pointer; registers.program_counter = initial_pc();
set_processor_state(state); registers.supervisor_stack_pointer = stack_pointer;
});
}
void set_registers(std::function<void(InstructionSet::M68k::RegisterSet &)> func) {
auto state = m68000_.get_state();
func(state.registers);
m68000_.set_state(state);
} }
void will_perform(uint32_t, uint16_t) { void will_perform(uint32_t, uint16_t) {
@ -107,10 +116,6 @@ class RAM68000: public CPU::MC68000Mk2::BusHandler {
return m68000_.get_state(); return m68000_.get_state();
} }
void set_processor_state(const CPU::MC68000Mk2::State &state) {
m68000_.decode_from_state(state.registers);
}
auto &processor() { auto &processor() {
return m68000_; return m68000_;
} }