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https://github.com/TomHarte/CLK.git
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Adds the final (!) set of missing MOVEs.
This commit is contained in:
Thomas Harte
parent
99981751a2
commit
f67d7f1db5
@ -2435,13 +2435,13 @@ struct ProcessorStorageConstructor {
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// MOVE <ea>, -(An)
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//
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case bw2(Dn, PreDec): // MOVE.bw Dn, -(An)
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case bw2(Dn, PreDec): // MOVE.bw [An/Dn], -(An)
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op(Action::PerformOperation);
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op( decrement_action | MicroOp::DestinationMask,
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seq("np nw", { a(destination_register) }, !is_byte_access));
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break;
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case l2(Dn, PreDec): // MOVE.l Dn, -(An)
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case l2(Dn, PreDec): // MOVE.l [An/Dn], -(An)
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op(Action::PerformOperation);
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op( int(Action::Decrement2) | MicroOp::DestinationMask, seq("np") );
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op( int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask, seq("nw- nW", { ea(1), ea(1) } ));
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@ -2468,26 +2468,26 @@ struct ProcessorStorageConstructor {
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op(int(Action::Decrement2) | MicroOp::DestinationMask );
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break;
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case bw2(XXXl, PreDec):
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case bw2(XXXl, PreDec): // MOVE.bw (xxx).l, -(An)
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op(Action::None, seq("np"));
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case bw2(XXXw, PreDec):
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case bw2(d16An, PreDec):
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case bw2(d8AnXn, PreDec):
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case bw2(d16PC, PreDec):
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case bw2(d8PCXn, PreDec):
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case bw2(XXXw, PreDec): // MOVE.bw (xxx).w, -(An)
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case bw2(d16An, PreDec): // MOVE.bw (d16, An), -(An)
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case bw2(d8AnXn, PreDec): // MOVE.bw (d8, An, Xn), -(An)
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case bw2(d16PC, PreDec): // MOVE.bw (d16, PC), -(An)
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case bw2(d8PCXn, PreDec): // MOVE.bw (d8, PC, Xn), -(An)
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op( address_action_for_mode(combined_source_mode) | MicroOp::SourceMask,
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seq(pseq("np nr", combined_source_mode), { ea(0) }, !is_byte_access ));
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op(Action::PerformOperation);
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op(decrement_action | MicroOp::DestinationMask, seq("np nw", { a(destination_register) }, !is_byte_access));
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break;
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case l2(XXXl, PreDec):
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case l2(XXXl, PreDec): // MOVE.l (xxx).w, -(An)
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op(Action::None, seq("np"));
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case l2(XXXw, PreDec):
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case l2(d16An, PreDec):
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case l2(d8AnXn, PreDec):
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case l2(d16PC, PreDec):
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case l2(d8PCXn, PreDec):
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case l2(XXXw, PreDec): // MOVE.l (xxx).l, -(An)
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case l2(d16An, PreDec): // MOVE.l (d16, An), -(An)
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case l2(d8AnXn, PreDec): // MOVE.l (d8, An, Xn), -(An)
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case l2(d16PC, PreDec): // MOVE.l (d16, PC), -(An)
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case l2(d8PCXn, PreDec): // MOVE.l (d8, PC, Xn), -(An)
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op( address_action_for_mode(combined_source_mode) | MicroOp::SourceMask,
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seq(pseq("np nR+ nr", combined_source_mode), { ea(0), ea(0) } ));
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op(Action::PerformOperation);
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@ -2496,13 +2496,13 @@ struct ProcessorStorageConstructor {
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op(int(Action::Decrement2) | MicroOp::DestinationMask);
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break;
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case bw2(Imm, PreDec):
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case bw2(Imm, PreDec): // MOVE.bw #, -(An)
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op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np"));
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op(Action::PerformOperation);
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op(decrement_action | MicroOp::DestinationMask, seq("np nw", { a(destination_register) }, !is_byte_access));
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break;
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case l2(Imm, PreDec):
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case l2(Imm, PreDec): // MOVE.l #, -(An)
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op(Action::None, seq("np"));
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op(int(Action::AssembleLongWordDataFromPrefetch) | MicroOp::SourceMask, seq("np"));
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op(Action::PerformOperation);
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@ -2518,104 +2518,98 @@ struct ProcessorStorageConstructor {
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// MOVE <ea>, (d8, PC, Xn)
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//
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case bw2(Dn, d16An): // MOVE.bw Dn, (d16, An)
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case bw2(Dn, d8AnXn): // MOVE.bw Dn, (d8, An, Xn)
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case bw2(Dn, d16PC): // MOVE.bw Dn, (d16, PC)
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case bw2(Dn, d8PCXn): // MOVE.bw Dn, (d8, PC, Xn)
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#define bw2d(s) bw2(s, d16An): case bw2(s, d8AnXn): case bw2(s, d16PC): case bw2(s, d8PCXn)
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#define l2d(s) l2(s, d16An): case l2(s, d8AnXn): case l2(s, d16PC): case l2(s, d8PCXn)
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case bw2d(Dn): // MOVE.bw [An/Dn], (d16, An)/(d8, An, Xn)/(d16, PC)/(d8, PC, Xn)
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op(calc_action_for_mode(combined_destination_mode) | MicroOp::DestinationMask, seq(pseq("np", combined_destination_mode)));
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op(Action::PerformOperation, seq("nw np", { ea(1) }, !is_byte_access));
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break;
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case l2(Dn, d16An): // MOVE.l Dn, (d16, An)
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case l2(Dn, d8AnXn): // MOVE.l Dn, (d8, An, Xn)
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case l2(Dn, d16PC): // MOVE.l Dn, (d16, PC)
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case l2(Dn, d8PCXn): // MOVE.l Dn, (d8, PC, Xn)
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case l2d(Dn): // MOVE.l [An/Dn], (d16, An)/(d8, An, Xn)/(d16, PC)/(d8, PC, Xn)
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op(calc_action_for_mode(combined_destination_mode) | MicroOp::DestinationMask, seq(pseq("np", combined_destination_mode)));
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op(Action::PerformOperation, seq("nW+ nw np", { ea(1), ea(1) }));
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break;
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case bw2(Ind, d16An): // MOVE.bw (An)[+], (d16, An)
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case bw2(Ind, d8AnXn): // MOVE.bw (An)[+], (d8, An, Xn)
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case bw2(Ind, d16PC): // MOVE.bw (An)[+], (d16, PC)
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case bw2(Ind, d8PCXn): // MOVE.bw (An)[+], (d8, PC, Xn)
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case bw2d(Ind): // MOVE.bw (An)[+], (d16, An)/(d8, An, Xn)/(d16, PC)/(d8, PC, Xn)
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op(calc_action_for_mode(combined_destination_mode) | MicroOp::DestinationMask, seq("nr", { a(ea_register) }, !is_byte_access));
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op(Action::PerformOperation, seq(pseq("np nw np", combined_destination_mode), { ea(1) }, !is_byte_access));
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break;
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case l2(Ind, d16An): // MOVE.l (An)[+], (d16, An)
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case l2(Ind, d8AnXn): // MOVE.l (An)[+], (d8, An, Xn)
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case l2(Ind, d16PC): // MOVE.l (An)[+], (d16, PC)
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case l2(Ind, d8PCXn): // MOVE.l (An)[+], (d8, PC, Xn)
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case l2d(Ind): // MOVE.l (An)[+], (d16, An)/(d8, An, Xn)/(d16, PC)/(d8, PC, Xn)
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op(int(Action::CopyToEffectiveAddress) | MicroOp::SourceMask);
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op(calc_action_for_mode(combined_destination_mode) | MicroOp::DestinationMask, seq("nR+ nr", { ea(0), ea(0) }));
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op(Action::PerformOperation, seq(pseq("np nW+ nw np", combined_destination_mode), { ea(1), ea(1) }));
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break;
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// TODO: PreDec, d16An, d8AnXn, s16PC, d8PCXn.
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// (4, 5, 6, 12, 13)
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case bw2(XXXl, d16An): // MOVE.bw (xxx).l, (d16, An)
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case bw2(XXXl, d8AnXn): // MOVE.bw (xxx).l, (d8, An, Xn)
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case bw2(XXXl, d16PC): // MOVE.bw (xxx).l, (d16, PC)
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case bw2(XXXl, d8PCXn): // MOVE.bw (xxx).l, (d16, PC, Xn)
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op(Action::None, seq("np"));
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case bw2(XXXw, d16An): // MOVE.bw (xxx).w, (d16, An)
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case bw2(XXXw, d8AnXn): // MOVE.bw (xxx).w, (d8, An, Xn)
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case bw2(XXXw, d16PC): // MOVE.bw (xxx).w, (d16, PC)
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case bw2(XXXw, d8PCXn): // MOVE.bw (xxx).w, (d16, PC, Xn)
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op(address_assemble_for_mode(combined_source_mode) | MicroOp::SourceMask, seq("np nr", { ea(0) }, !is_byte_access));
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op(calc_action_for_mode(combined_destination_mode) | MicroOp::DestinationMask);
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op(Action::PerformOperation, seq(pseq("np nw np", combined_destination_mode), { ea(1) }, !is_byte_access));
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case bw2d(PreDec): // MOVE.bw -(An), (d16, An)/(d8, An, Xn)/(d16, PC)/(d8, PC, Xn)
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op(decrement_action | MicroOp::SourceMask, seq("n nr", { a(ea_register) }, !is_byte_access));
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op(Action::PerformOperation);
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op(calc_action_for_mode(combined_destination_mode) | MicroOp::DestinationMask, seq("np nw np", { ea(1) }, !is_byte_access));
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break;
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case l2(XXXl, d16An): // MOVE.l (xxx).l, (d16, An)
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case l2(XXXl, d8AnXn): // MOVE.l (xxx).l, (d8, An, Xn)
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case l2(XXXl, d16PC): // MOVE.l (xxx).l, (d16, PC)
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case l2(XXXl, d8PCXn): // MOVE.l (xxx).l, (d16, PC, Xn)
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op(Action::None, seq("np"));
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case l2(XXXw, d16An): // MOVE.l (xxx).w, (d16, An)
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case l2(XXXw, d8AnXn): // MOVE.l (xxx).w, (d8, An, Xn)
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case l2(XXXw, d16PC): // MOVE.l (xxx).w, (d16, PC)
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case l2(XXXw, d8PCXn): // MOVE.l (xxx).w, (d16, PC, Xn)
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op(address_assemble_for_mode(combined_source_mode) | MicroOp::SourceMask, seq("np nR+ nr", { ea(0), ea(0) }));
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op(calc_action_for_mode(combined_destination_mode) | MicroOp::DestinationMask);
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op(Action::PerformOperation, seq(pseq("np nW+ nw np", combined_destination_mode), { ea(1), ea(1) }));
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case l2d(PreDec): // MOVE.l -(An), (d16, An)/(d8, An, Xn)/(d16, PC)/(d8, PC, Xn)
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op(decrement_action | MicroOp::SourceMask, seq("n"));
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op(int(Action::CopyToEffectiveAddress) | MicroOp::SourceMask, seq("nR+ nr", { ea(0), ea(0) }));
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op(Action::PerformOperation);
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op(calc_action_for_mode(combined_destination_mode) | MicroOp::DestinationMask, seq("np nW+ nw np", { ea(1), ea(1) }));
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break;
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case bw2(Imm, d16An): // MOVE.bw #, (d16, An)
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case bw2(Imm, d16PC): // MOVE.bw #, (d16, PC)
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case bw2(Imm, d8PCXn): // MOVE.bw #, (d8, PC, Xn)
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case bw2(Imm, d8AnXn): // MOVE.bw #, (d8, An, Xn)
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case bw2d(XXXl): // MOVE.bw (xxx).l, (d16, An)/(d8, An, Xn)/(d16, PC)/(d8, PC, Xn)
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op(Action::None, seq("np"));
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case bw2d(XXXw): // MOVE.bw (xxx).w, (d16, An)/(d8, An, Xn)/(d16, PC)/(d8, PC, Xn)
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case bw2d(d16An): // MOVE.bw (d16, An), (d16, An)/(d8, An, Xn)/(d16, PC)/(d8, PC, Xn)
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case bw2d(d8AnXn): // MOVE.bw (d8, An, Xn), (d16, An)/(d8, An, Xn)/(d16, PC)/(d8, PC, Xn)
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case bw2d(d16PC): // MOVE.bw (d16, PC), (d16, An)/(d8, An, Xn)/(d16, PC)/(d8, PC, Xn)
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case bw2d(d8PCXn): // MOVE.bw (d8, PC, xn), (d16, An)/(d8, An, Xn)/(d16, PC)/(d8, PC, Xn)
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op(address_action_for_mode(combined_source_mode) | MicroOp::SourceMask, seq(pseq("np nr", combined_source_mode), { ea(0) }, !is_byte_access));
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op(Action::PerformOperation);
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op(calc_action_for_mode(combined_destination_mode) | MicroOp::SourceMask, seq(pseq("np nw np", combined_destination_mode), { ea(1) }, !is_byte_access));
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break;
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case l2d(XXXl): // MOVE.l (xxx).l, (d16, An)/(d8, An, Xn)/(d16, PC)/(d8, PC, Xn)
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op(Action::None, seq("np"));
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case l2d(XXXw): // MOVE.l (xxx).w, (d16, An)/(d8, An, Xn)/(d16, PC)/(d8, PC, Xn)
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case l2d(d16An): // MOVE.l (d16, An), (d16, An)/(d8, An, Xn)/(d16, PC)/(d8, PC, Xn)
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case l2d(d8AnXn): // MOVE.l (d8, An, Xn), (d16, An)/(d8, An, Xn)/(d16, PC)/(d8, PC, Xn)
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case l2d(d16PC): // MOVE.l (d16, PC), (d16, An)/(d8, An, Xn)/(d16, PC)/(d8, PC, Xn)
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case l2d(d8PCXn): // MOVE.l (d8, PC, xn), (d16, An)/(d8, An, Xn)/(d16, PC)/(d8, PC, Xn)
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op(address_action_for_mode(combined_source_mode) | MicroOp::SourceMask, seq(pseq("np nR+ nr", combined_source_mode), { ea(0), ea(0) }));
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op(Action::PerformOperation);
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op(calc_action_for_mode(combined_destination_mode) | MicroOp::SourceMask, seq(pseq("np nW+ nw np", combined_destination_mode), { ea(1), ea(1) }));
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break;
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case bw2d(Imm): // MOVE.bw #, (d16, An)/(d8, An, Xn)/(d16, PC)/(d8, PC, Xn)
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op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::SourceMask, seq("np"));
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op(calc_action_for_mode(combined_destination_mode) | MicroOp::DestinationMask, seq(pseq("np", combined_destination_mode)));
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op(Action::PerformOperation, seq("nw np", { ea(1) }, !is_byte_access));
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break;
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case l2(Imm, d16An): // MOVE.l #, (d16, An)
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case l2(Imm, d16PC): // MOVE.l #, (d16, PC)
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case l2(Imm, d8PCXn): // MOVE.l #, (d8, PC, Xn)
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case l2(Imm, d8AnXn): // MOVE.l #, (d8, An, Xn)
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case l2d(Imm): // MOVE.l #, (d16, An)/(d8, An, Xn)/(d16, PC)/(d8, PC, Xn)
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op(Action::None, seq("np"));
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op(int(Action::AssembleLongWordDataFromPrefetch) | MicroOp::SourceMask, seq("np"));
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op(calc_action_for_mode(combined_destination_mode) | MicroOp::DestinationMask, seq(pseq("np", combined_destination_mode)));
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op(Action::PerformOperation, seq("nW+ nw np", { ea(1), ea(1) }));
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break;
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#undef bw2d
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#undef l2d
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//
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// MOVE <ea>, (xxx).W
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// MOVE <ea>, (xxx).L
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//
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case bw2(Dn, XXXl): // MOVE.bw Dn, (xxx).L
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case bw2(Dn, XXXl): // MOVE.bw [An/Dn], (xxx).L
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op(Action::None, seq("np"));
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case bw2(Dn, XXXw): // MOVE.bw Dn, (xxx).W
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case bw2(Dn, XXXw): // MOVE.bw [An/Dn], (xxx).W
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op(address_assemble_for_mode(combined_destination_mode) | MicroOp::DestinationMask, seq("np"));
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op(Action::PerformOperation, seq("nw np", { ea(1) }, !is_byte_access));
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break;
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case l2(Dn, XXXl): // MOVE.l Dn, (xxx).L
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case l2(Dn, XXXl): // MOVE.l [An/Dn], (xxx).L
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op(Action::None, seq("np"));
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case l2(Dn, XXXw): // MOVE.l Dn, (xxx).W
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case l2(Dn, XXXw): // MOVE.l [An/Dn], (xxx).W
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op(address_assemble_for_mode(combined_destination_mode) | MicroOp::DestinationMask, seq("np"));
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op(Action::PerformOperation, seq("nW+ nw np", { ea(1), ea(1) }));
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break;
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@ -2676,56 +2670,56 @@ struct ProcessorStorageConstructor {
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seq("nW+ nw np np", { ea(1), ea(1) }));
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break;
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case bw2(d16PC, XXXw):
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case bw2(d16An, XXXw):
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case bw2(d8PCXn, XXXw):
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case bw2(d8AnXn, XXXw):
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case bw2(d16PC, XXXw): // MOVE.bw (d16, PC), (xxx).w
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case bw2(d16An, XXXw): // MOVE.bw (d16, An), (xxx).w
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case bw2(d8PCXn, XXXw): // MOVE.bw (d8, PC, Xn), (xxx).w
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case bw2(d8AnXn, XXXw): // MOVE.bw (d8, An, Xn), (xxx).w
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op(calc_action_for_mode(combined_source_mode) | MicroOp::SourceMask, seq(pseq("np nr", combined_source_mode), { ea(0) }, !is_byte_access));
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op(Action::PerformOperation);
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op(int(Action::AssembleWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("np nw np", { ea(1) }, !is_byte_access));
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break;
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case bw2(d16PC, XXXl):
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case bw2(d16An, XXXl):
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case bw2(d8PCXn, XXXl):
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case bw2(d8AnXn, XXXl):
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case bw2(d16PC, XXXl): // MOVE.bw (d16, PC), (xxx).l
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case bw2(d16An, XXXl): // MOVE.bw (d16, An), (xxx).l
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case bw2(d8PCXn, XXXl): // MOVE.bw (d8, PC, Xn), (xxx).l
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case bw2(d8AnXn, XXXl): // MOVE.bw (d8, An, Xn), (xxx).l
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op(calc_action_for_mode(combined_source_mode) | MicroOp::SourceMask, seq(pseq("np np nr", combined_source_mode), { ea(0) }, !is_byte_access));
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op(Action::PerformOperation);
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op(int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("np nw np", { ea(1) }, !is_byte_access));
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break;
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case l2(d16PC, XXXw):
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case l2(d16An, XXXw):
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case l2(d8PCXn, XXXw):
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case l2(d8AnXn, XXXw):
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case l2(d16PC, XXXw): // MOVE.l (d16, PC), (xxx).w
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case l2(d16An, XXXw): // MOVE.l (d16, An), (xxx).w
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case l2(d8PCXn, XXXw): // MOVE.l (d8, PC, Xn), (xxx).w
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case l2(d8AnXn, XXXw): // MOVE.l (d8, An, Xn), (xxx).w
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op(calc_action_for_mode(combined_source_mode) | MicroOp::SourceMask, seq(pseq("np nR+ nr", combined_source_mode), { ea(0), ea(0) }));
|
||||
op(Action::PerformOperation);
|
||||
op(int(Action::AssembleWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("np nW+ nw np", { ea(1), ea(1) }));
|
||||
break;
|
||||
|
||||
case l2(d16PC, XXXl):
|
||||
case l2(d16An, XXXl):
|
||||
case l2(d8PCXn, XXXl):
|
||||
case l2(d8AnXn, XXXl):
|
||||
case l2(d16PC, XXXl): // MOVE.l (d16, PC), (xxx).l
|
||||
case l2(d16An, XXXl): // MOVE.l (d16, An), (xxx).l
|
||||
case l2(d8PCXn, XXXl): // MOVE.l (d8, PC, Xn), (xxx).l
|
||||
case l2(d8AnXn, XXXl): // MOVE.l (d8, An, Xn), (xxx).l
|
||||
op(calc_action_for_mode(combined_source_mode) | MicroOp::SourceMask, seq(pseq("np np nR+ nr", combined_source_mode), { ea(0), ea(0) }));
|
||||
op(Action::PerformOperation);
|
||||
op(int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("np nW+ nw np", { ea(1), ea(1) }));
|
||||
break;
|
||||
|
||||
case bw2(Imm, XXXw): // MOVE.bw #, (xxx).w
|
||||
case bw2(Imm, XXXw): // MOVE.bw #, (xxx).w
|
||||
op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::DestinationMask, seq("np"));
|
||||
op(Action::PerformOperation);
|
||||
op(int(Action::AssembleWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("np nw np", { ea(1) }, !is_byte_access));
|
||||
break;
|
||||
|
||||
case bw2(Imm, XXXl): // MOVE.bw #, (xxx).l
|
||||
case bw2(Imm, XXXl): // MOVE.bw #, (xxx).l
|
||||
storage_.instructions[instruction].source = &storage_.destination_bus_data_[0];
|
||||
op(int(Action::AssembleWordDataFromPrefetch) | MicroOp::DestinationMask, seq("np np"));
|
||||
op(Action::PerformOperation);
|
||||
op(int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("np nw np", { ea(1) }));
|
||||
break;
|
||||
|
||||
case l2(Imm, XXXw): // MOVE.l #, (xxx).w
|
||||
case l2(Imm, XXXw): // MOVE.l #, (xxx).w
|
||||
storage_.instructions[instruction].source = &storage_.destination_bus_data_[0];
|
||||
op(int(Action::None), seq("np"));
|
||||
op(int(Action::AssembleLongWordDataFromPrefetch) | MicroOp::DestinationMask, seq("np"));
|
||||
@ -2733,7 +2727,7 @@ struct ProcessorStorageConstructor {
|
||||
op(int(Action::AssembleWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("np nW+ nw np", { ea(1), ea(1) }));
|
||||
break;
|
||||
|
||||
case l2(Imm, XXXl): // MOVE.l #, (xxx).l
|
||||
case l2(Imm, XXXl): // MOVE.l #, (xxx).l
|
||||
storage_.instructions[instruction].source = &storage_.destination_bus_data_[0];
|
||||
op(int(Action::None), seq("np"));
|
||||
op(int(Action::AssembleLongWordDataFromPrefetch) | MicroOp::DestinationMask, seq("np np"));
|
||||
@ -2741,48 +2735,48 @@ struct ProcessorStorageConstructor {
|
||||
op(int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("np nW+ nw np", { ea(1), ea(1) }));
|
||||
break;
|
||||
|
||||
case bw2(XXXw, XXXw): // MOVE.bw (xxx).w, (xxx).w
|
||||
case bw2(XXXw, XXXw): // MOVE.bw (xxx).w, (xxx).w
|
||||
op(int(Action::AssembleWordAddressFromPrefetch) | MicroOp::SourceMask, seq("np nr", { ea(0) }, !is_byte_access));
|
||||
op(Action::PerformOperation, seq("np"));
|
||||
op(int(Action::AssembleWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("nw np", { ea(1) }, !is_byte_access));
|
||||
continue;
|
||||
|
||||
case bw2(XXXl, XXXw): // MOVE.bw (xxx).l, (xxx).w
|
||||
case bw2(XXXl, XXXw): // MOVE.bw (xxx).l, (xxx).w
|
||||
op(int(Action::None), seq("np"));
|
||||
op(int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::SourceMask, seq("np nr", { ea(0) }, !is_byte_access));
|
||||
op(Action::PerformOperation);
|
||||
op(int(Action::AssembleWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("np nw np", { ea(1) }, !is_byte_access));
|
||||
break;
|
||||
|
||||
case bw2(XXXw, XXXl): // MOVE.bw (xxx).w, (xxx).L
|
||||
case bw2(XXXw, XXXl): // MOVE.bw (xxx).w, (xxx).L
|
||||
op(int(Action::AssembleWordAddressFromPrefetch) | MicroOp::SourceMask, seq("np nr", { ea(0) }, !is_byte_access));
|
||||
op(Action::PerformOperation, seq("np"));
|
||||
op(int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("nw np np", { ea(1) }, !is_byte_access));
|
||||
continue;
|
||||
|
||||
case bw2(XXXl, XXXl): // MOVE.bw (xxx).l, (xxx).l
|
||||
case bw2(XXXl, XXXl): // MOVE.bw (xxx).l, (xxx).l
|
||||
op(int(Action::None), seq("np"));
|
||||
op(int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::SourceMask, seq("np nr", { ea(0) }, !is_byte_access));
|
||||
op(Action::PerformOperation, seq("np"));
|
||||
op(int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("nw np np", { ea(1) }, !is_byte_access));
|
||||
break;
|
||||
|
||||
case l2(XXXw, XXXw): // MOVE.l (xxx).w (xxx).w
|
||||
case l2(XXXw, XXXw): // MOVE.l (xxx).w (xxx).w
|
||||
op(int(Action::AssembleWordAddressFromPrefetch) | MicroOp::SourceMask, seq("np nR+ nr", { ea(0), ea(0) }));
|
||||
op(Action::PerformOperation);
|
||||
op(int(Action::AssembleWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("np nW+ nw np", { ea(1), ea(1) }));
|
||||
break;
|
||||
|
||||
case l2(XXXl, XXXw): // MOVE.l (xxx).l, (xxx).w
|
||||
case l2(XXXl, XXXw): // MOVE.l (xxx).l, (xxx).w
|
||||
op(int(Action::None), seq("np"));
|
||||
op(int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::SourceMask, seq("np nR+ nr", { ea(0), ea(0) }));
|
||||
op(Action::PerformOperation);
|
||||
op(int(Action::AssembleWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("np nW+ nw np", { ea(1), ea(1) }));
|
||||
break;
|
||||
|
||||
case l2(XXXl, XXXl): // MOVE.l (xxx).l, (xxx).l
|
||||
case l2(XXXl, XXXl): // MOVE.l (xxx).l, (xxx).l
|
||||
op(int(Action::None), seq("np"));
|
||||
case l2(XXXw, XXXl): // MOVE.l (xxx).w (xxx).l
|
||||
case l2(XXXw, XXXl): // MOVE.l (xxx).w (xxx).l
|
||||
op(address_action_for_mode(combined_source_mode) | MicroOp::SourceMask, seq("np nR+ nr", { ea(0), ea(0) }));
|
||||
op(Action::PerformOperation, seq("np"));
|
||||
op(int(Action::AssembleLongWordAddressFromPrefetch) | MicroOp::DestinationMask, seq("nW+ nw np np", { ea(1), ea(1) }));
|
||||
|
||||
Loading…
Reference in New Issue
Block a user