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Implements RTI, corrects TAY.

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This commit is contained in:
Thomas Harte 2020-10-08 18:06:11 -04:00
parent 0418f51ef2
commit f8004d7096
2 changed files with 15 additions and 3 deletions
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16
Processors/65816/Implementation/65816Implementation.hpp
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@ -467,7 +467,7 @@ template <typename BusHandler> void Processor<BusHandler>::run_for(const Cycles
break;
case TAY:
LD(x_, a_.full, x_masks_);
LD(y_, a_.full, x_masks_);
flags_.set_nz(y_.full, x_shift_);
break;
@ -483,7 +483,7 @@ template <typename BusHandler> void Processor<BusHandler>::run_for(const Cycles
//
// Jumps.
// Jumps and returns.
//
case JML:
@ -513,6 +513,16 @@ template <typename BusHandler> void Processor<BusHandler>::run_for(const Cycles
pc_ = instruction_buffer_.value;
break;
case RTI:
pc_ = uint16_t(data_buffer_.value >> 8);
flags_.set(uint8_t(data_buffer_.value));
if(!emulation_flag_) {
program_bank_ = (data_buffer_.value & 0xff000000) >> 8;
assert(false); // Extra flags to unpack!
}
break;
//
// Block moves.
//
@ -729,7 +739,7 @@ template <typename BusHandler> void Processor<BusHandler>::run_for(const Cycles
// REP, SEP,
// XCE, XBA,
// STP, WAI,
// RTI, RTL,
// RTL,
// TCD, TCS, TDC, TSC
default:

2
Processors/65816/Implementation/65816Storage.cpp
View File

@ -649,6 +649,8 @@ struct CPU::WDC65816::ProcessorStorageConstructor {
target(CyclePull); // New PCL
target(CyclePull); // New PCH
if(!is8bit) target(CyclePull); // PBR
// TODO: 8bit check here doesn't actually work, it needs to be an is-emulation-mode check.
// New operation needed, I think.
target(OperationPerform); // [RTI] — to unpack the fields above.
}