diff --git a/Processors/65816/Implementation/65816Implementation.hpp b/Processors/65816/Implementation/65816Implementation.hpp index 6aa9543b8..ff2e997ec 100644 --- a/Processors/65816/Implementation/65816Implementation.hpp +++ b/Processors/65816/Implementation/65816Implementation.hpp @@ -467,7 +467,7 @@ template void Processor::run_for(const Cycles break; case TAY: - LD(x_, a_.full, x_masks_); + LD(y_, a_.full, x_masks_); flags_.set_nz(y_.full, x_shift_); break; @@ -483,7 +483,7 @@ template void Processor::run_for(const Cycles // - // Jumps. + // Jumps and returns. // case JML: @@ -513,6 +513,16 @@ template void Processor::run_for(const Cycles pc_ = instruction_buffer_.value; break; + case RTI: + pc_ = uint16_t(data_buffer_.value >> 8); + flags_.set(uint8_t(data_buffer_.value)); + + if(!emulation_flag_) { + program_bank_ = (data_buffer_.value & 0xff000000) >> 8; + assert(false); // Extra flags to unpack! + } + break; + // // Block moves. // @@ -729,7 +739,7 @@ template void Processor::run_for(const Cycles // REP, SEP, // XCE, XBA, // STP, WAI, - // RTI, RTL, + // RTL, // TCD, TCS, TDC, TSC default: diff --git a/Processors/65816/Implementation/65816Storage.cpp b/Processors/65816/Implementation/65816Storage.cpp index 7ef6e22eb..b03fb70a6 100644 --- a/Processors/65816/Implementation/65816Storage.cpp +++ b/Processors/65816/Implementation/65816Storage.cpp @@ -649,6 +649,8 @@ struct CPU::WDC65816::ProcessorStorageConstructor { target(CyclePull); // New PCL target(CyclePull); // New PCH if(!is8bit) target(CyclePull); // PBR + // TODO: 8bit check here doesn't actually work, it needs to be an is-emulation-mode check. + // New operation needed, I think. target(OperationPerform); // [RTI] — to unpack the fields above. }